Hynix Semiconductor Inc.

Sumco Corporation

Hanyang Hak Won Co., Ltd.

Won Mo Lee

Jea Gun Park

Takeo Katoh

Yong Soo Choi

Kyung Ho Hwang

Un Gyu Paik

Sung Jun Kim

Hyun Goo Kang

A slurry composition for chemical-mechanical polishing capable of compensating nanotopography effect present on the surface of a wafer, and a method for planarizing the surface of a semiconductor device that utilizes the same are disclosed. The slurry composition of the present invention is aimed at compensating the nanotopography effect during chemical mechanical polishing process of the oxide layer formed on the surface of the wafer, and contains abrasive particles and an additive, wherein the size of the abrasive particles and the concentration of the additive are controlled within predetermined ranges in order to control the deviation of thickness (OTD) of the oxide layer below a certain level after the chemical mechanical polishing process.

Slurry composition for chemical-mechanical polishing capable of compensating nanotopography effect and method for planarizing surface of semiconductor device using the same

Provided are a semiconductor device, adapted to be capable of fabricating the device having improved resistance characteristic by decreasing dishing of solid phase epitaxy (SPE) silicon during planarization in a landing plug forming process via use of SPE silicon, and a method of manufacturing the same. The method of manufacturing a semiconductor device in accordance with the present invention comprises, forming a plurality of gates on a semiconductor substrate; forming an interlayer dielectric film thereon, such that the gates are embedded; selectively etching the interlayer dielectric film to open a landing plug-forming region; depositing SPE silicon, such that the opened landing plug-forming region in the interlayer dielectric film is embedded; implanting boron ions into the SPE silicon; and annealing the resulting boron ion-implanted structure.

Semiconductor device and method of manufacturing the same

Disclosed herein is a chemical mechanical polishing (CMP) method for manufacturing a semiconductor device, comprising performing partial ion implantation of dopants at different concentrations into a plurality of at least two divided regions of a wafer having a planarization-target film, and subjecting the partially ion implanted-wafer to a chemical mechanical polishing process. In accordance with the present invention, non-uniformity of the removal rate in a chemical mechanical polishing process is countervailed by dopants which are implanted at different concentrations via partial ion implantation, and thereby it is possible to polish the target film at a uniform removal rate.

Chemical mechanical polishing method for manufacturing semiconductor device

Growing community of inventors

Seoul, South Korea

Won Mo Lee