Samsung Electronics Co., Ltd.

Won-Kyung Park

Satoru Yamada

Jun-Hee Lim

Kyo-Suk Chae

Ki-Jae Hur

Joon Soo Han

Hyeong-sun Hong

Young Jin Choi

Hyuk-Joon Kwon

Se-Young Kim

Sungho Jang

Junhee Lim

Jun-ho Park

Seung-Uk Han

Hyoung-ho Ko

A semiconductor memory device includes a bit line sense amplifier, a first column select gate, and a second column select gate. The bit line sense amplifier senses an electric potential difference between a bit line and a complementary bit line during a sensing operation for memory cells. The first column select gate transfers an electric potential on the bit line to a local sense amplifier based on a column select signal. The second column select gate transfers an electric potential on the complementary bit line to the local sense amplifier based on the column select signal. The first and second column select gates have different current drive abilities to compensate a difference in bit line interconnection resistance.

Semiconductor memory device compensating difference of bitline interconnection resistance

A semiconductor device includes an active region defined on a substrate, a gate electrode disposed on the active region and covering two adjacent corners of the active region, a drain area formed in the active region adjacent to a first side of the gate electrode, and a source area formed in the active region adjacent to a second side of the gate electrode. The first and second sides of the gate electrode are spaced apart from each other, and the first side has a bent shape.

Semiconductor device having wave gate

A semiconductor device is provided. A cell region is disposed in a substrate. The cell region includes a memory cell. A peripheral region is disposed in the substrate. The peripheral region is adjacent to the cell region. The peripheral region has a trench isolation, a first active region and a second active region. The trench isolation is interposed between the first active region and the second active region. A common gate pattern is disposed on the peripheral region. The common gate pattern extends in a first direction and partially overlaps the first active region, the second active region and the trench isolation. A buried conductive pattern is enclosed by the trench isolation. The buried conductive pattern extends in a second direction crossing the first direction. A top surface of the buried conductive pattern is lower than a bottom surface of the common gate pattern.

Semiconductor device and method of forming the same

A semiconductor device includes a substrate including a memory cell region and a peripheral region and a field pattern including an insulating region disposed on a nitride liner in a trench in the substrate adjacent an active region. The field pattern and the active region extend in parallel through the cell and peripheral regions. The device also includes a transistor in the peripheral region including a source/drain region in the active region. The device further includes an insertion pattern including an elongate conductive region disposed in the substrate and extending along a boundary between the field pattern and the active region in the peripheral region. Fabrication methods are also described.

Semiconductor devices with peripheral region insertion patterns

A semiconductor device includes a sub word line driver. A first sub word line and a second sub word line transmit an operation signal to a memory cell. A main word line optionally sends the operation signal to the first sub word line and the second sub word line. A switching transistor is disposed between the first sub word line and the second sub word line. A gate of the switching transistor is connected the main word line.

Semiconductor device including sub word line driver

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Seoul, South Korea

Won-Kyung Park