Amkor Technology, Inc.

Amkor Technology Singapore Holding Pte. Ltd.

Won Joon Kang

Eun Sook Sohn

Gi Jeong Kim

Tae Kyung Hwang

Do Hyung Kim

Min Woo Lee

Bong Chan Kim

Chan Ha Hwang

A method for providing an electronic package structure includes providing a substrate having a die pad having a die pad top surface and an opposing die pad bottom surface, leads laterally spaced apart from the die pad, and a substrate encapsulant interposed between the die pad and the leads and includes a substrate top surface and an opposing substrate bottom surface. The substrate encapsulant is provided such that the die pad and the leads protrude outward from the substrate bottom surface. The method includes providing an electronic device having opposing major surfaces and a pair of opposing outer edges. The method includes connecting the electronic device to the substrate such that one major surface of the electronic device is spaced apart from the die pad top surface and upper surfaces of the leads, and the outer edges overlap an opposing pair of the leads.

Electronic package structure with reduced vertical stress regions

Electronic package structure with improved board level reliability

An electronic package includes a lead frame structure having one or more structural features configured to improve board level reliability. In one embodiment, the structural feature comprises lead frame protrusions extending outward from the electronic package, which are configured to laterally engage solder structures used to attach the electronic package to a next level of assembly. In another embodiment, conductive bumps are attached to exposed portions of the lead frame in advance of next level assembly processes. In a further embodiment, the lead frame comprises laterally separated contact points for attaching an electron die and for attaching the electronic package to a next level of assembly.

Chip-scale electronic package structure with conductive connective element having increased surface area and laterally spaced connection points for improved connectivity

In accordance with the present invention, there is provided multiple embodiments of a reduced profile stackable semiconductor package. The semiconductor package comprises a substrate having at least one semiconductor die attached thereto. The semiconductor die is also electrically connected to the substrate by a plurality of conductive wires. A package body defining opposed top and bottom surfaces and a side surface at least partially encapsulates the substrate, the conductive wires and the semiconductor die. The package body is formed such that at least portions of the conductive wires are exposed in the top surface thereof. The package body may include a groove formed in the top surface thereof, with at least portions of the conductive wires being exposed in the groove. In this instance, conductive material layers may be disposed within the groove and electrically connected to the exposed portions of respective ones of the conductive wires, with solder pads further bring electrically connected to respective ones of the conductive material layers and at least partially residing within the groove.

Reduced profile stackable semiconductor package

Growing community of inventors

Seoul, South Korea

Won Joon Kang