Skhynix Inc.

Hynix Semiconductor Inc.

Toshiba Memory Corporation

Kabushiki Kaisha Toshiba

Won-Joon Choi

Guk-Cheon Kim

Yang-Kon Kim

Jong-Koo Lim

Bo-Mi Lee

Ki-Seon Park

Cha-Deok Dong

Ku-Youl Jung

Heung-Jae Cho

Seung-Mo Noh

Jae-Hong Kim

Yong-Soo Kim

Moon-Sig Joo

Jeong-Myeong Kim

Min-Suk Lee

Jae-Heon Kim

Chan-Sik Park

Choi-Dong Kim

Daisuke Watanabe

Toshihiko Nagase

Young-Wook Lee

Kazuya Sawada

Makoto Nagamine

Ki-Hong Lee

Youngmin Eeh

Beom-Yong Kim

Eun-Seok Choi

Se-Yun Lim

Sang-Bum Lee

Seung Mo Noh

Koji Ueda

Hong-Seon Yang

Jung-Ryul Ahn

Young-Min Eeh

Jun-Yeol Cho

This technology provides a method for fabricating an electronic device. A method for fabricating an electronic device including a variable resistance element, which includes a free layer having a variable magnetization direction; a pinned layer having a first non-variable magnetization direction, and including first ferromagnetic materials and a first spacer layer interposed between adjacent two first ferromagnetic materials among the first ferromagnetic materials; a tunnel barrier layer interposed between the free layer and the pinned layer; a magnetic correction layer having a second magnetization direction which is anti-parallel to the first magnetization direction; and a third spacer layer interposed between the magnetic correction layer and the pinned layer, and providing an anti-ferromagnetic exchange coupling between the magnetic correction layer and the pinned layer.

Electronic device and method for fabricating the same

Methods, systems, and devices are disclosed for implementing semiconductor memory using variable resistance elements for storing data. In one aspect, an electronic device is provided to comprise a semiconductor memory unit including: a substrate; an interlayer dielectric layer disposed over the substrate; and a variable resistance element including a seed layer formed over the interlayer dielectric layer, a first magnetic layer formed over the seed layer, a tunnel barrier layer formed over the first magnetic layer, and a second magnetic layer formed over the tunnel barrier layer, wherein the seed layer includes a conductive material having a metallic property and an oxygen content of 1% to approximately 10%.

Provided is a method for fabricating an electronic device including a variable resistance element which includes a free layer formed over a substrate and having a changeable magnetization direction, a pinned layer having a pinned magnetization direction, a tunnel barrier layer interposed between the free layer and the pinned layer, and a magnetic correction layer suitable for reducing the influence of a stray field generated by the pinned layer. The method may include: cooling the substrate; and forming the magnetic correction layer over the cooled substrate.

Disclosed are an electronic device comprising a semiconductor memory. The semiconductor memory includes a variable resistance element including a free layer having a variable magnetization direction; a pinned layer having a fixed magnetization direction; and a tunnel barrier layer interposed between the free layer and the pinned layer, wherein the free layer includes: a first free layer adjacent to the tunnel barrier layer and having a perpendicular magnetic anisotropy at an interface with the tunnel barrier layer; and a second free layer spaced apart from the tunnel barrier layer by the first free layer and having a saturation magnetization lower than a saturation magnetization of the first free layer.

Electronic device including a semiconductor memory having a variable resistance element including two free layers

Electronic devices and systems having semiconductor memory are provided. In one implementation, for example, an electronic device may include a substrate; an under layer disposed over the substrate and including conductive hafnium silicate; a free layer disposed over the under layer and having a variable magnetization direction; a tunnel barrier layer disposed over the free layer; and a pinned layer disposed over the tunnel barrier layer and having a pinned magnetization direction, and wherein the free layer includes: a first ferromagnetic material; a second ferromagnetic material having a coercive force smaller than that of the first ferromagnetic material; and an amorphous spacer interposed between the first ferromagnetic material and the second ferromagnetic material.

Provided is an electronic device including a semiconductor memory. The semiconductor memory may include: an under layer including first and second metal layers and a barrier layer having a dual phase structure of different crystal structures and interposed between the first and second metal layers; a first magnetic layer positioned over the under layer and having a variable magnetization direction; a tunnel barrier layer positioned over the first magnetic layer; and a second magnetic layer positioned over the tunnel barrier layer and having a pinned magnetization direction, and the under layer may further include a barrier layer having a dual phase structure between the first and second metal layers.

An electronic device is provided to include a semiconductor memory that includes: a substrate including a first region and a second region different from the first region; an interlayer dielectric layer formed over the substrate; a first conductive pattern located over the first region and formed in the interlayer dielectric layer, the first conductive pattern including a planarized top surface with a top surface of the interlayer dielectric layer; a second conductive pattern located over the second region and formed in the interlayer dielectric layer, the second conductive pattern including at least a portion recessed below a top surface of the interlayer dielectric layer; a variable resistance pattern formed over the interlayer dielectric layer the variable resistance pattern having a bottom surface coupled to the first conductive pattern and exhibiting different resistance values; and a capping layer pattern formed over the variable resistance pattern.

This technology provides an electronic device. An electronic device in accordance with an implementation of this document may include a semiconductor memory, and the semiconductor memory may include: an under layer including a plurality of material layers having a different crystal structures; a first magnetic layer formed over the under layer and having a variable magnetization direction; a tunnel barrier layer formed over the first magnetic layer; and a second magnetic layer formed over the tunnel barrier layer and having a pinned magnetization direction.

Electronic device

This technology provides an electronic device. An electronic device in accordance with an implementation of this document may include a semiconductor memory for storing data, and the semiconductor memory may include a free layer having a variable magnetization direction; a pinned layer having a pinned magnetization direction; a tunnel barrier layer interposed between the free layer and the pinned layer; and an interface enhancement layer interposed between the tunnel barrier layer and the pinned layer, wherein the interface enhancement layer may include an Fe-rich first layer; a Co-rich second layer formed over the first layer; and a metal layer formed over the second layer.

Electronic devices having semiconductor memory with interface enhancement layer

Implementations of the disclosed technology provide an electronic device including a semiconductor memory, wherein the semiconductor memory includes: a magnetic tunnel junction (MTJ) structure including a free layer having a changeable magnetization direction, a pinned layer having a pinned magnetization direction, and a tunnel barrier layer sandwiched between the free layer and the pinned layer; and an under layer located under the MTJ structure, wherein the under layer includes a first under layer including a silicon-based alloy, and a second under layer located on the first under layer and including a metal.

Growing community of inventors

Icheon-si, South Korea

Won-Joon Choi