Micron Technology Incorporated

Won Joo Yun

Sang-Hoon Shin

Hyunui Lee

Jennifer E Taylor

William Chad Waldrop

Baekkyu Choi

Rajesh H Kariya

Jinha Hwang

Youngkwon Jo

Bhargav Kalva

An apparatus including reconfigurable interface circuits and associated systems and methods are disclosed herein. A reconfigurable interface circuit may include an output buffer and an input buffer coupled to a connector for respectively generating and receiving signals. The reconfigurable interface circuit may include a control circuit configured to control operation of the input and output buffers along with additional circuits to selectively implement one or more from a set of selectable communication settings.

Apparatus including reconfigurable interface and methods of manufacturing the same

Implementations described herein relate to various structures, integrated assemblies, and memory devices. In some implementations, a semiconductor package may include a substrate having a first plurality of substrate bond pads and a second plurality of substrate bond pads, and a semiconductor die having a first plurality of die bond pads and a second plurality of die bond pads. Each die bond pad, included in the first plurality of die bond pads, may be connected to a corresponding substrate bond pad, included in the first plurality of substrate bond pads, using bump bonding, and each die bond pad, included in the second plurality of die bond pads, may be connected to a corresponding substrate bond pad, included in the second plurality of substrate bond pads, using wire bonding.

Semiconductor package with hybrid wire bond and bump bond connections

A semiconductor device includes an interface configured to receive clock signals and data signals. The interface includes a dual-tail latch. The dual-tail latch includes a sensing stage configured to sense and to amplify a differential voltage between at least a portion of the data signals and another signal. The sensing stage includes a first node and a second node between which the amplified differential voltage is output from the sensing stage. The dual-tail latch also includes a latch stage configured to latch a first latched value and a second latched value based at least in part on the amplified differential voltage. Moreover, the differential voltage is based at least in part on a previous first value and a previous second value from the latch stage fed back to the sensing stage.

Systems and methods for improved dual-tail latch with load control

A semiconductor device includes a pair of transistors configured to implement buffering of input data to outputs. The semiconductor device also includes a first transistor configured to receive a common-mode of the outputs at a gate terminal of the first transistor. The semiconductor device also includes a current source configured to control a tail current from the pair of transistors. Additionally, the semiconductor device includes a second transistor configured to adjust the tail current based at least in part on changes in a reference voltage used by the pair of transistors to buffer the input data. Furthermore, the semiconductor device includes a third transistor configured to adjust the tail current based at least in part on changes in locally generated reference voltage based at least in part on a process and temperature variations.

Current-controlled buffer using analog bias

Systems and methods that may enable alignment of a receiver enable signal with one or more clocking signals. By aligning the receiver operations with the one or more clocking signals, a likelihood of a false or incorrect data capture may be reduced, which may improve operation of a memory system. Reducing a likelihood of incorrect data capture may increase an accuracy of a distortion correction operation of a decision feedback equalizer (DFE).

Synchronous input buffer enable for DFE operation

A semiconductor device may include one or more output drivers. An output driver may be adjusted for impedance matching by applying a body voltage to one or more transistors of the output driver. In some examples, the body voltage applied may be based on a comparison between a reference voltage and a voltage at an external terminal. In some examples, the semiconductor device may include a calibration circuit that includes a comparator and an up/down counter that, based on a signal from the comparator, generates a code indicating the body voltage to be applied. The body voltage may be applied by a voltage generator in some examples.

Apparatuses, systems, and methods for ZQ calibration

An apparatus including reconfigurable interface circuits and associated systems and methods are disclosed herein. An reconfigurable interface circuit may include an output buffer and an input buffer coupled to a connector for respectively generating and receiving signals. The reconfigurable interface circuit may include a control circuit configured to control operation of the input and output buffers along with additional circuits to selectively implement one or more from a set of selectable communication settings.

A keeper device is used in a hybrid loop unrolled DFE circuit to selectively output signals from equalizers corresponding to a specific possibility of the values of the previous bit (e.g., logical high or logical low) when DFE technique is not used. Those equalizers corresponding to possibilities other than the specific possibility of the values of the previous bit are disabled in the hybrid loop unrolled DFE circuit. As such, the hybrid loop unrolled DFE circuit saves power when the DFE technique is not used since only a portion of the total equalizers in the hybrid loop unrolled DFE circuit are powered.

Hybrid loop unrolled decision feedback equalizer architecture

Test input/output speed conversion and related apparatuses and methods are disclosed. An apparatus includes a glue circuit and a BIST circuit for core circuitry of an integrated circuit device. The, the BIST circuit includes a test interface, one or more inputs, and one or more outputs. The BIST circuit is configured to operate at a first speed. The glue circuit is configured to interface with the test interface, the one or more inputs, and the one or more outputs of the BIST circuit. The glue circuit is configured to convert between second speed test interface signals and second speed input/output signals operating at a second speed and first speed test interface signals and first speed input/output signals operating at the first speed. The second speed is different from the first speed.

Test input/output speed conversion and related apparatuses and methods

The present application is directed to signal delay control and related apparatuses, systems, and methods. An apparatus includes delay elements and control circuitry electrically connected to the delay elements. The delay elements are configured to receive skewed data signals and delay codes indicating delay quantities. The delay elements are also configured to provide delayed data signals delayed relative to the skewed data signals by the delay quantities. The control circuitry is configured to provide the delay codes, which are selected to reduce a timing skew of the delayed data signals relative to a timing skew of the skewed data signals. A system includes a first device, a second device including the apparatus, and transmission lines electrically connected between the first device and the second device. A method includes calibrating the delay codes.

Signal delay control and related apparatuses, systems, and methods

Methods for improving timing in memory devices are disclosed. A method may include sampling a command signal according to a clock signal to obtain standard-timing commands. The method may also include sampling the command signal according to an adjusted clock signal to obtain time-adjusted commands. The method may also include comparing the standard-timing commands and the time-adjusted commands. The method may also include determining an improved timing for the clock signal based on the comparison of the standard-timing commands and the time-adjusted commands. The method may also include adjusting the clock signal based on the improved timing. Associated systems and methods are also disclosed.

Growing community of inventors

Boise, ID, United States of America

Won Joo Yun