Samsung Electronics Co., Ltd.

Won-Joo Kim

Yoon-Dong Park

Suk-Pil Kim

Tae-Hee Lee

June-mo Koo

Sang-Moo Choi

Young-Gu Jin

Jae-woong Hyun

Seung-hoon Lee

Seung-Hwan Song

Tae-eung Yoon

Jung-Hoon Lee

Dae-kil Cha

Hyang-Shik Kong

Ju-Hwan Jung

Deok-kee Kim

Sung-Jae Byun

Kwon-Young Choi

Sun-Ae Seo

Young-Joon Rhee

Jung-hun Sung

Bong-Joo Kang

Seung-Taek Lim

Jong-jin Lee

Shin-Wook Yi

Kyoung-Iae Cho

Bum-Gee Baek

In-jae Song

Hyoung-Soo Ko

Young-soo Park

Hoon Tae Kim

I-hun Song

Kyu-Charn Park

Min-Ho Kim

Sang-Bo Lee

Jin-Kyung Lee

Sang-min Shin

Young-gu Jin

Gi-Sang Lee

In-sung Joe

Byoung-Iyong Choi

Dong-wook Kwon

Kyung-Il Kim

Choong-rae Cho

Jin-Wuk Choi

Hyuk-soon Choi

Sam-jong Choi

Kyoo-Chul Cho

Yoon-dong Park

Yong-Koo Kyoung

Gi-jung Kim

Seoung-hyun Kim

A mobile system may comprise a three-dimensional (3D) image sensor on a first surface of the mobile system configured to perform a first sensing to detect proximity of a subject and a second sensing to recognize a gesture of the subject by acquiring distance information for the subject; and/or a display device on the first surface of the mobile system to display results of the first sensing and the second sensing. A mobile system may comprise a light source unit; a plurality of depth pixels; and/or a plurality of color pixels. The light source unit, the plurality of depth pixels, or the plurality of color pixels may be activated based on an operation mode of the mobile system.

Mobile systems including image sensors, methods of operating image sensors, and methods of operating mobile systems

Disclosed are a sensing pixel and an image sensor including the same. The sensing pixel includes a determination region, which includes one or more floating body transistors, and an integration region that is adjacent to a floating body region of one of the one or more floating body transistors, absorbs light to generate an electron-hole pair including an electron and a positive hole, and transfers the electron or the positive hole to the floating body region of the one floating body transistor.

Sensing pixel and image sensor including the same

A unit pixel of a depth sensor includes a light-receiver configured to perform photoelectric conversion of an incident light to output an electrical signal and at least two sensors adjacent to the light-receiver to receive the electrical signal from the light-receiver such that a line connecting the sensors forms an angle greater than zero degrees with respect to a first line, the first line passing through a center of the light-receiver in a horizontal direction.

Unit pixels, depth sensors and three-dimensional image sensors including the same

A three-dimensional (3D) CMOS image sensor (CIS) that sufficiently absorbs incident infrared-rays (IRs) and includes an infrared-ray (IR) receiving unit formed in a thin epitaxial film, thereby being easily manufactured using a conventional CIS process, a sensor system including the 3D CIS, and a method of manufacturing the 3D CIS, the 3D CIS including an IR receiving part absorbing IRs incident thereto by repetitive reflection to produce electron-hole pairs (EHPs); and an electrode part formed on the IR receiving part and collecting electrons produced by applying a predetermined voltage thereto.

3D CMOS image sensors, sensor systems including the same

Provided is a method of operating a semiconductor device, wherein an operating mode is set by adjusting timing of a voltage pulse or by adjusting a voltage level of the voltage pulse.

Method of operating semiconductor device

Semiconductor devices and semiconductor device manufacturing methods. The semiconductor device manufacturing methods may form a memory cell having a silicon on insulator (SOI) structure only in one or more localized regions of a bulk semiconductor substrate by use selective etching. Accordingly, a different bias voltage may be applied to a peripheral device than to a memory cell having the SOI structure.

Semiconductor devices and semiconductor device manufacturing methods

Provided are a non-volatile memory devices having a stacked structure, and a memory card and a system including the same. A non-volatile memory device may include a substrate. A stacked NAND cell array may have at least one NAND set and each NAND set may include a plurality of NAND strings vertically stacked on the substrate. At least one signal line may be arranged on the substrate so as to be commonly coupled with the at least one NAND set.

Non-volatile memory device having stacked structure, and memory card and electronic system including the same

Provided are a non-volatile memory device, which may have a stacked structure and may be easily integrated at increased density, and a method of fabricating and using the non-volatile memory device. The non-volatile memory device may include at least one pair of first electrode lines. At least one second electrode line may be between the at least one pair of first electrode lines. At least one data storage layer may be between the at least one pair of first electrode lines and the at least one second electrode line and may locally store a resistance change.

Non-volatile memory devices having data storage layer

Semiconductor devices and semiconductor apparatuses including the same are provided. The semiconductor devices include a body region disposed on a semiconductor substrate, gate patterns disposed on the semiconductor substrate and on opposing sides of the body region, and first and second impurity doped regions disposed on an upper surface of the body region. The gate patterns may be separated from the first and second impurity doped regions by, or greater than, a desired distance, such that the gate patterns do not to overlap the first and second impurity doped regions in a direction perpendicular to the first and second impurity doped regions.

Semiconductor devices and semiconductor apparatuses including the same

Antifuse structures, antifuse arrays, methods of manufacturing, and methods of operating the same are provided. An antifuse structure includes bitlines formed as first diffusing regions within a semiconductor substrate, an insulation layer formed on the bitlines, and wordlines formed on the insulation layer. An antifuse array includes a plurality of antifuse structures arranged in an array.

Antifuse structures, antifuse array structures, methods of manufacturing the same

Methods of operating nonvolatile memory devices are provided. In a method of operating a nonvolatile memory device including a plurality of memory cells, recorded data is stabilized by inducing a boosting voltage on a channel of a memory cell in which the recorded data is recorded. The memory cell is selected from a plurality of memory cells and the boosting voltage on the channel of the selected memory cell is induced by a channel voltage of at least one memory cell connected to the selected memory cell.

Methods of operating nonvolatile memory devices

A method of operating a semiconductor device including a memory cell of a 1-T DRAM is provided in which a gate voltage level in a hold mode is adjusted to adjust a data sensing margin of the semiconductor device.

Method of operating semiconductor devices

A method of operating a semiconductor device is provided including applying a constant source voltage to a source line.

Semiconductor apparatuses and methods of operating the same

A non-volatile memory device having a stack structure, and a method of operating the non-volatile memory device In which the non-volatile memory device includes a plurality of variable resistors arranged in at least one layer. At least one layer selection bit line and a plurality of bit lines coupled to the plurality of the variable resistors are provided. A plurality of selection transistors coupled between the plurality of the bit lines and the plurality of the variable resistors are provided.

Non-volatile memory device and method of operating the same

Growing community of inventors

Hwaseong-si, South Korea

Won-Joo Kim