Samsung Electronics Co., Ltd.

Sungkyunkwan University

Won-jong Yoo

Jae-young Choi

Jong-min Kim

Young-jun Park

Seung-hwan Lee

Jun-hee Choi

Byeong-Yun Nam

Byong-sun Ju

Hyoun-woo Kim

Ji-a Lee

Chang-ho Ra

Tian-zi Shen

Huamin Li

Min-sup Choi

Xiao Chi Liu

A tunneling device may include a tunnel barrier layer, a first material layer including a first conductivity type two-dimensional material on a first surface of the tunnel barrier layer and a second material layer including a second conductivity type two-dimensional material on a second surface of the tunnel barrier layer. The tunneling device may use a tunneling current through the tunnel barrier layer between the first material layer and the second material layer.

Tunneling devices and methods of manufacturing the same

A photodetector includes a substrate, a graphene layer disposed on the substrate, a first electrode disposed on the graphene layer, and a second electrode disposed on the graphene layer, where the first and second electrodes are spaced apart from each other, and where each of the first and second electrodes comprises a complex transparent electrode. The complex transparent electrode of the first electrode may have a different composition from the complex transparent electrode of the second electrode.

Graphene-based photodetector including complex transparent electrode, method of manufacturing the same, and device including the same

An anti-reflection structure using surface plasmons and a high-k dielectric material, and a method of manufacturing the anti-reflection structure. The anti-reflection structure may include a high-k dielectric layer formed on a substrate, the high-k dielectric layer configured to allow incident light to pass therethrough, and a nano-material layer on the high-k dielectric layer. The high-k dielectric layer may include at least one of zirconium oxide (ZrO), hafnium oxide (HfO), titanium oxide (TiO), tantalum oxide (TaO), lanthanum oxide (LaO), yttrium oxide (YO) and aluminum oxide (AlO).

Anti-reflection structure using surface plasmon and high-K dielectric material and method of manufacturing the anti-reflection structure

A method for etching a platinum (Pt) layer of a semiconductor device is provided which improves the etching slope of a sidewall of the platinum layer used as a storage node of the semiconductor device. The semiconductor device consists of a semiconductor substrate including a bottom layer on which various other layers are formed. Specifically, according to this invention, a Pt layer is formed on a bottom layer of a semiconductor substrate. An adhesive layer is then formed on the Pt layer while a mask layer is formed on the adhesive layer. After formation of the various layers, the mask layer and adhesive layer are patterned using an etching process to form a mask pattern and an adhesive layer mask pattern, respectively. The semiconductor substrate is then heated and an etching process is performned on the Pt layer using the mask pattern and the adhesive layer mask pattern to form etching slope sidewalls of the Pt layer having etching slopes close to vertical. Accordingly, the Pt electrodes of the semiconductor device of the present invention have a finer pattern than those of the prior art. Finally, overetching is done to remove the mask pattern.

Method for etching Pt film of semiconductor device

Growing community of inventors

Suwon-si, South Korea

Won-jong Yoo