Samsung Electronics Co., Ltd.

Won-Jin Kim

Young-Wook Park

Jeong-Do Ryu

Jin-Woo Kim

Yong-Seok Kim

Joon-Hee Lee

Seong-Ho Kim

Hyun-Suk Kim

Jong-Won Kim

Byung-Hong Chung

Hyun Kyu Park

Jeong-lim Nam

Jin-Gi Hong

Yong-Won Cha

Ji-Young Min

Guk-Hyon Yon

Yong-Kwan Cho

Jin-Yong Jang

Phil-Koo Yeo

Byoung-Ik Kang

Young-Ho Koh

Chang-Seob Kim

The present disclosure relates to a sensor network, machine type communication (MTC), machine-to-machine (M2M) communication, and technology for Internet of Things (IoT). The present disclosure provides intelligent services based on a variety of technologies, such as a smart home, a smart building, a smart city, a smart car, a connected car, a health care, a digital education, a smart retail, security and safety services. An apparatus and method for executing a task of an electronic device are provided. The apparatus includes a communication interface configured to receive state information associated with the electronic device from the electronic device, and a processor configured to determine whether to execute a specific task in the electronic device or a mobile terminal based on the state information about the electronic device and state information about the mobile terminal, and to indicate a result of the determination to the electronic device through the communication interface.

Apparatus and method for executing task of electronic device

A wiring structure of a semiconductor device may include an insulation interlayer on a substrate, the insulation interlayer having a linear first trench having a first width and a linear second trench having a second width, the linear second trench being in communication with a lower portion of the linear first trench, the first width being wider than the second width, and a conductive layer pattern in the linear first and second trenches.

Wiring structure of a semiconductor device, method of forming the wiring structure, non-volatile memory device including the wiring structure, and method of manufacturing the non-volatile memory device

A memory device includes a charge trapping layer on a substrate, an insulating layer on the substrate adjacent to the charge trapping layer and exposing an upper surface of the charge trapping layer, a dielectric layer on the exposed charge trapping layer and on the insulating layer, and an electrode on the dielectric layer, the electrode corresponding to the charge trapping layer.

Charge trapping type semiconductor memory device and method of manufacturing the same

There is provided a method of chemical mechanical polishing (CMP) and a method of fabricating a semiconductor device using the same. The method includes forming a layer to be polished on a semiconductor substrate including a normally polished region and a dished region, and forming a dishing (i.e., over-polishing)-preventing layer on the layer to be polished in the region where dishing may occur. Then, the layer to be polished is polished while dishing thereof is prevented using the dishing-preventing layer. Accordingly, the dishing-preventing layer is formed in the region where the dishing (i.e., over-polishing) may occur, so that the dishing is prevented from occurring in a region where pattern density is low and a pattern size is large in the process of CMP.

Method of chemical mechanical polishing and method of fabricating semiconductor device using the same

Methods of fabricating a semiconductor device can include forming at least one layer on a first and a second side of a semiconductor substrate. Portions of the at least one layer may be removed on the first side of the semiconductor substrate to form a pattern of the at least one layer on the first side of the substrate while the at least one layer is maintained on the second side of the substrate. A capping layer can be formed on the pattern of the at least one layer on the first side of the substrate and on the at least one layer on the second side of the semiconductor substrate. The capping layer can be removed on the second side of the semiconductor substrate, thereby exposing the at least one layer on the second side of the substrate while maintaining the capping layer on the first side of the substrate. The at least one layer can be removed on the second side of the semiconductor substrate, while the capping layer and the pattern of the at least one layer is maintained on the first side of the semiconductor substrate. A portion of the capping layer can be removed on the first side of the semiconductor substrate.

Methods of fabricating a semiconductor substrate for reducing wafer warpage

Methods of forming an electronic device including a substrate and a raised pattern on the substrate are provided. For example, a first insulating layer may be formed on the raised pattern and on the substrate. More particularly, forming the first insulating layer may include forming a first portion of the first insulating layer using a first processing condition and forming a second portion of the first insulating layer using a second processing condition. After forming the first insulating layer including the first and second portions, portions of the first insulating layer may be removed to expose portions of the raised pattern while maintaining portions of the first insulating layer on the substrate. After removing portions of the first insulating layer, a second insulating layer may be formed on the exposed portions of the raised pattern and on the maintained portions of the first insulating layer.

Methods of forming integrated circuit devices including insulation layers

Methods are provided for forming integrated circuit devices. A spin on glass (SOG) insulating layer is formed on an integrated circuit substrate. The SOG insulating layer includes sidewalls that define contact holes therein and spacers are formed on the sidewalls of the SOG insulating layer. Integrated circuit devices are also provided. The integrated circuit devices include an integrated circuit substrate, a spin on glass (SOG) insulating layer on the integrated circuit substrate. The SOG insulating layer includes sidewalls that define contact holes therein and spacers are provided on sidewalls of the SOG insulating layer.

Methods of fabricating integrated circuit devices having spin on glass (SOG) insulating layers and integrated circuit devices fabricated thereby

A metal via contact of a semiconductor device and a method for fabricating the same, wherein the method includes sequentially forming a first insulating layer, a low dielectric SOG (Spin On Glass) layer, a second insulating layer and a silicon oxynitride (SiON) layer on a semiconductor substrate forming a photoresist pattern, using the photoresist pattern as an etching mask and wet etching the silicon oxynitride layer and a portion of the second insulating layer, using the same photoresist pattern as an etching mask and anisotropically etching remainder second insulating layer, the low dielectric SOG layer and the first insulating layer to form a via hole exposing a predetermined portion of the semiconductor substrate, removing the photoresist pattern, using radio frequency (RF) etching to remove a reverse slope of the via hole and forming a metal plug in the via hole.

Growing community of inventors

Gyeonggi-do, South Korea

Won-Jin Kim