Samsung Electronics Co., Ltd.

Won-il Ryu

Soo-doo Chae

Hee-soon Chae

Chung-woo Kim

Byong-man Kim

Jo-won Lee

Moon-kyung Kim

Se-wook Yoon

Ju-hyung Kim

Byung-ki Kim

In a silicon-oxide-nitride-oxide-silicon (SONOS) memory device and a method of manufacturing the same, a SONOS memory device includes a semiconductor substrate, an insulating layer deposited on the semiconductor substrate, an active layer formed on a predetermined region of the insulating layer and divided into a source region, a drain region, and a channel region, a first side gate stack formed at a first side of the channel region, and a second side gate stack formed at a second side of the channel region opposite the first side of the channel region. In the SONOS memory device, at least two bits of data may be stored in each SONOS memory device, thereby allowing the integration density of the semiconductor memory device to be increased without increasing an area thereof.

SONOS memory device having side gate stacks and method of manufacturing the same

In a method for manufacturing a single electron memory device including a single electron storage element in a gate lamination pattern formed on a nano-scale channel region of a MOSFET, formation of the gate lamination pattern includes sequentially forming a lower layer and a single electron storage medium for storing a single electron tunneling through the lower layer on a substrate, forming an upper layer including a plurality of quantum dots on the single electron storage medium, forming a gate electrode layer on the upper layer to be in contact with the plurality of quantum dots, and patterning the lower layer, the single electron storage medium, the upper layer, and the gate electrode layer, in reverse order.

Method for manufacturing a single electron memory device having quantum dots between gate electrode and single electron storage element

A nonvolatile silicon/oxide/nitride/silicon/nitride/oxide/silicon (SONSNOS) structure memory device includes a first insulating layer and a second insulating layer stacked on a channel of a substrate, a first dielectric layer and a second dielectric layer formed on the first insulating layer and under the second insulating layer, respectively, and a group IV semiconductor layer, silicon quantum dots, or metal quantum dots interposed between the first dielectric layer and the second dielectric layer. The provided SONSNOS structure memory device improves a programming rate and the capacity of the memory.

Nonvolatile silicon/oxide/nitride/silicon/nitride/oxide/silicon memory

A single electron memory device including quantum dots between a gate electrode and a single electron storage element and a method for manufacturing the same, wherein the single electron memory device includes a substrate on which a nano-scale channel region is formed between a source and a drain, and a gate lamination pattern including quantum dots on the channel region. The gate lamination pattern includes a lower layer formed on the channel region, a single electron storage medium storing a single electron tunneling through the lower layer formed on the lower layer, an upper layer including quantum dots formed on the single electron storage medium, and a gate electrode formed on the upper layer to be in contact with the quantum dots.

Single electron memory device comprising quantum dots between gate electrode and single electron storage element and method for manufacturing the same

A method for etching a metal layer on a scale of nano meters, includes preparing a substrate on which a metal layer is formed, positioning a micro tip over the metal layer, generating an electron beam from the micro tip by applying a predetermined voltage between the metal layer and the micro tip, and etching the surface of the metal layer into a predetermined pattern with the electron beam. Accordingly, it is possible to form an etched pattern by applying a negative bias to a micro tip without applying a strong mechanical force to the micro tip, and heating/melting the metal layer with the use of an electron beam emitted from the micro tip which is negative-biased.

Method for etching metal layer on a scale of nanometers

A split gate type flash memory having an active region that improves an endurance characteristic along with program/erase efficiency, wherein the split gate type flash memory provides for improvement in the endurance characteristic and program/erase efficiency by making the width of an active region in a portion in which a source is overlapped by a floating gate as large as possible.

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Seoul, South Korea

Won-il Ryu