Samsung Electronics Co., Ltd.

Won-Il Bae

Kyo-Min Sohn

Byung-chul Kim

Jun-hyung Kim

Min-Soo Kim

Sung-Hoon Kim

Seong-Jin Jang

Young-Sik Kim

Jung-Hwan Choi

Chul-woo Park

Young-Soo Sohn

Jong-Pil Son

Chul-Woo Park

Sung-Chul Park

Uk-Song Kang

Hoon Ryu

Jei-Hwan Yoo

Sang-Joon Hwang

Min-Sang Park

Hi-Choon Lee

Myeong-O Kim

Yong-Gyu Chu

Won-Chang Jung

Ho-Seok Seol

Sung-Min Yim

Joo-Sun Choi

Du-yeul Kim

Chi-Hwan Lee

Jong-Wan Kim

A method of operating a semiconductor memory device including a memory cell array and an error correction circuit is provided as follows. A write command, main data and an address are received from a memory controller. An error correction data unit is provided to the error correction circuit. The error correction data unit includes the main data. At least one parity bit is generated based on the error correction data unit. A write operation is performed, in response to the write command, on a target page selected by the address so that the at least one parity bit and the main data are written to the target page and the at least one parity data is written later than the main data to the target page.

Semiconductor memory device and method for controlling write timing of parity data

A semiconductor memory device includes a memory structure including a first integrated circuit chip and a plurality of second integrated circuit chips stacked on each other, the first integrated circuit chip is interposed between a pair of the plurality of second integrated circuit chips, an interface unit disposed on the first integrated circuit chip, the memory structure is connected to a third circuit through the interface unit, and the interface unit transfers operation signals to the first integrated circuit chip and the plurality of second integrated circuit chips, at least one inter-chip interconnector connected with the interface unit and the first integrated circuit chip and the plurality of second integrated circuit chips, and an external interconnector connected with the interface unit and the third circuit.

Semiconductor memory device including stacked chips and memory module having the same

In a method of operating a memory device, a command and a first address from a memory controller are received. A read code word including a first set of data corresponding to the first address, a second set of data corresponding to a second address and a read parity data is read from a memory cell array of the memory device. Corrected data are generated by operating error checking and correction (ECC) using an ECC circuit based on the read cord word.

Method of operating memory device and methods of writing and reading data in memory device

Provided is a method of detecting a concentrated address of a semiconductor device using an n-bit address. The method includes dividing the n-bit address into k groups, wherein each of n and k is an integer equal to or greater than 2, for each group of the k groups, detecting one or more concentrated sub addresses corresponding to the group, and generating at least one concentrated address by combining the one or more concentrated sub addresses for the k groups.

Concentrated address detecting method of semiconductor device and concentrated address detecting circuit using the same

A method of configuring a semiconductor integrated circuit (IC) includes arranging a circuit region in the center of a unit cell. Capacitor/resistor regions are arranged along the left and right edge portions of the unit cell. The capacitor/resistor regions include a plurality of active resistors having the same length and a capacitor having a width equal to the length of the plurality of active resistors. In addition, a first conductive layer is arranged longitudinally in each of the capacitor/resistor regions so as to contact the left and right edge portions of the unit cell.

Method of configuring a semiconductor integrated circuit involving capacitors having a width equal to the length of active resistors

In an embodiment, a semiconductor memory device includes a clock latency that can be controlled responsive to whether or not an output order of burst data is reordered. The semiconductor memory device may comprise a control unit and a latency control unit. The control unit may generate a latency control signal having a logic level that varies depending on whether or not an output order of burst data is reordered. The latency control unit may control a latency value in response to the latency control signal. The semiconductor memory device and the method of controlling the latency value responsive to a reordering of the burst data allow for an optimally fast memory access time.

Semiconductor memory device and method for controlling clock latency according to reordering of burst data

A semiconductor memory device includes a first row of pads including a first plurality of data input/output (I/O) pads; a second row of pads including a second plurality of data I/O pads; and a first I/O multiplexer associated with the first row of pads and providing first output data only to at least one data I/O pad of the first row of pads, even after a data I/O mode of the semiconductor memory device has changed. The semiconductor memory device also includes a second I/O multiplexer associated with the second row of pads and providing second output data only to at least one data I/O pad of the second row of pads, even after the data I/O mode has changed.

Semiconductor memory device comprising two rows of pads

A voltage generating circuit for a semiconductor memory device. The voltage generating circuit includes a multi-boosting unit for stepping up a power supply voltage, a transfer transistor connected to a final boosting node of the multi-boosting unit and an output node, and a charge-sharing element, electrically connected to the final boosting node and a gate node of the transfer transistor, enabled during at least a part of the period the power supply voltage is stepped-up by the multi-boosting unit and performing charge sharing between the final boosting node and the gate node of the transfer transistor.

Voltage generating circuit, semiconductor memory device comprising the same, and voltage generating method

A semiconductor device package includes a plurality of semiconductor memory devices whose address input terminals are commonly connected to the external address input pins of the package, and an internal address generating device for using an address signal applied through at least one of the address input pins to select one of the memory devices to perform a read/write data operation. Only the selected memory device is enabled to perform the read/write operation on a memory cell corresponding to the received address signal. The external pin configuration of the semiconductor device package is compatible with a conventional memory board layout.

Semiconductor memory device

A semiconductor memory device includes a memory cell array and a differential amplifying and latching circuit for latching and outputting each of signal pairs output from the memory cell array in case of a first latency operation, and for amplifying a voltage difference of each of the signal pairs output from the memory cell array in case of a second latency operation.

Semiconductor memory device and data read method thereof

Refreshing of a portion of a DRAM device is bypassed when carrying out a refreshing operation on the DRAM device. By bypassing the refreshing of a portion of the DRAM device when carrying out a refreshing operation, the operational speed of the DRAM device and of systems that use the DRAM device can be increased, and/or the power consumption thereof can be decreased. More specifically, graphic memory apparatus include a DRAM device that is divided into a frame buffer zone that supplies pixel data for a display and at least one other zone, such as a z buffer and/or a texture storing zone. Refreshing of the frame buffer zone is bypassed when carrying out a refreshing operation on the DRAM device. In a preferred embodiment, indications of a starting DRAM address and an ending DRAM address for the frame buffer may be stored. A refreshing operation is performed only on those DRAM addresses that fall outside the starting address and the ending address.

Methods and apparatus for bypassing refreshing of selected portions of DRAM devices

A semiconductor memory device has a sub word line driver structure and includes a main word line decoder driver, an address programming circuit, and a redundant main word line decoder driver. When row address bit signals are input, the main word line decoder driver drives a main word line corresponding to the row address bit signals regardless of a row replacement with redundant rows. If the row address bit signals correspond to programmed defective row address bit signals, the address programming circuit generates a redundant row select signal, in response to which the activated main word line is deactivated and a redundant main word line is activated. According to the redundant row replacement scheme of the present invention, access time is reduced without an increase of a layout area.

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Seongnam-si, South Korea

Won-Il Bae