Samsung Electronics Co., Ltd.

Won-Ho Choi

Dong-Hun Lee

Young-Kyun Jeong

Ji-Hun Shin

Chang-Eun Kang

Seog-Heon Ham

Wun-Ki Jung

Kwi-Sung Yoo

Hyeok-jong Lee

Min-ho Kwon

Jin-Woo Kim

June-Hee Lee

Min-Sun Keel

Jung-Hoon Chun

Eun-young Jin

Young-Tae Jang

Jae-jung Park

Hyuk-Bin Kwon

Dae-Hwa Paik

A line memory device includes a plurality of memory cells, a data line pair, a sense amplifier and an output unit. The plurality of memory cells are disposed adjacent to each other in a line. The data line pair is coupled to the memory cells to sequentially transfer memory data bits stored in the memory cells to the sense amplifier. The sense amplifier is configured to amplify the memory data bits that are sequentially transferred through the data line pair by corresponding delay times which are different from each other. The output unit samples an output of the sense amplifier to sequentially output retimed data bits of the memory data bits in response to a read clock signal. The read clock signal has a cyclic period which is less than a maximum delay time among the delay times.

Line memory device and image sensor including the same

A data interface includes a first sampler sampling a first bitset and a second sampler sampling a second bitset. The first bitset includes a first bit which is included in a first image data and a third bit which is included in a second image, and the second bitset includes a second bit which is included in the first image data and is a higher-order bit than the first bit and a fourth bit which is included in the second image data and is a higher-order bit than the third bit. The data interface further includes a clock generator configured to adjust a sampling timing of the first and second bitsets based on a multi-phase clock, and a clock data recovery (CDR) circuit shared by the first sampler, the second sampler and configured to output the multi-phase clock to the clock generator.

Data interface and data transmission method

A data transmission circuit includes a data output unit (DOU) connected to a positive data transmission line and a negative data transmission line. The DOU generates a recovered data signal based on data signals communicated via the positive and negative data transmission lines. Data signal driving units are respectively connected at different points along the positive and negative data transmission lines, where each data signal driving unit generates and provides a positive data signal and a negative data signal based on a data input signal and a data transmission distance between the data signal driving unit and the data output unit.

Data transmission circuit, image sensor including the same

An integrated circuit counter includes a cascaded chain of bit counters, which are collectively configured to count a number of first edges of a counter input signal received at an input thereof and output the count as a counter output signal. The cascaded chain includes at least two bit counters, which are: (i) configured to support both counter and buffer modes of operation, and (ii) responsive to respective bypass control bit signals having values that specify whether a corresponding one of the at least two bit counters is disposed in the counter or buffer mode of operation.

Counter circuit and image sensor including the same

A counter circuit includes a first counter and a second counter. The first counter is configured to count a first counter clock signal which toggles with a first frequency to generate upper (N&#x2212;M)-bit signals of N-bit counter output signals, in response to a first counting enable signal based on a first comparison signal during a coarse counting interval. N and M are natural numbers, N is greater than M, and M is greater than or equal to 3. The second counter is configured to count a second counter clock signal which toggles with a second frequency which is higher than the first frequency to generate lower M-bit signals of the N-bit counter output signals, in response to a second counting enable signal based on the first comparison signal and a second comparison signal during a fine counting interval which follows the coarse counting interval.

Counter circuit, analog-to-digital converter, and image sensor including the same and method of correlated double sampling

A line driving circuit in which a signal characteristic is improved and a semiconductor device including the same are provided. The semiconductor device includes: a line controller arranged in a first portion of at least one line; a first driver arranged in the first portion and configured to output through the at least one line a first signal according to a control of the line controller; and a second driver arranged in a second portion of the at least one line and configured to output through the at least one line a second signal according to a level of the first signal.

Line driving circuit improving signal characteristic and semiconductor device including the same

A sampling circuit samples an input signal by using at least one switch, at least one capacitor, an amplifier, and a clamp block connected between an output terminal and a negative input terminal of the amplifier. The clamp block prevents a difference between a voltage level of the output terminal of the amplifier and a voltage level of the negative input terminal of the amplifier during sampling from exceeding a maximum voltage difference.

Sampling circuit and image signal amplifying circuit each including feedback clamp block and image sensor including the image signal amplifying circuit

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Suwon-si, South Korea

Won-Ho Choi