Sandisk Technologies Inc.

Western Digital Technologies, Inc.

Micron Technology Incorporated

Other

Won Ho Choi

Martin Lueker-Boden

Pi-Feng Chiu

Wen Ma

Zvonimir Z Bandic

Minghai Qin

Young-Suk Choi

Tung Thanh Hoang

Yongjune Kim

Jay Kumar

Cyril Guyot

Yuval Cassuto

Gerrit Jan Hemink

Ward M Parkinson

Federico Nardi

Yoocharn Jeon

Raj K Ramanujan

Matthew Alan Prather

James E O'Toole

Randall J Rooney

Anand Kulkarni

Erik V Pohlmann

Jongyeon Kim

Scott Schlachter

Martin Lueker-boden

Exemplary methods and apparatus are disclosed that implement super-sparse image/video compression by storing image dictionary elements within a cross-bar resistive random access memory (ReRAM) array (or other suitable cross-bar NVM array). In illustrative examples, each column of the cross-bar ReRAM array stores the values for one dictionary element (such as one 4×4 dictionary element). Methods and apparatus are described for training (configuring) the cross-bar ReRAM array to generate and store the dictionary elements by sequentially applying patches from training images to the array using an unstructured Hebbian training procedure. Additionally, methods and apparatus are described for compressing an input image by applying patches from the input image to the ReRAM array to read out cross-bar column indices identifying the columns storing the various dictionary elements that best fit the image. This may be done in parallel using a set of ReRAM arrays.

Non-volatile cross-bar memory with on-chip processing circuitry

Devices and methods include transmitting loopback signals for monitoring operation of a memory device. In some embodiments, a memory device may receive a system clock signal from a host device and may generate an internal clock signal based at least in part on the system clock signal. In some embodiments, the memory device may generate a loopback signal based at least in part on the internal clock signal and may transmit the loopback signal via a loopback datapath associated with the memory device. A host device may compare the internal clock signal and the system clock signal to determine a fidelity of the internal clock signal. Termination values of the memory device may be adjusted based on the determined fidelity of the internal clock signal.

Loopback datapath for clock quality detection

Methods, systems, and devices for initializing memory systems are described. A memory system may transmit, to a host system over a first channel, signaling indicative of a first set of values for a set of parameters associated with communicating information over a second channel between a storage device of the memory system and a memory device of the memory system. The host system may transmit, to the memory system, additional signaling associated with the first set of values for the set of parameters. For instance, the host system may transmit a second set of values for the set of parameters, an acknowledgement to use the first set of values, or a command to perform a training operation on the second channel to identify a second set of values for the set of parameters. The memory system may communicate the information over the second channel based on the additional signaling.

Initializing memory systems

Anon-volatile memory structure capable of storing weights for layers of a deep neural network (DNN) and perform an inferencing operation within the structure is presented. An in-array multiplication can be performed between multi-bit valued inputs, or activations, for a layer of the DNN and multi-bit valued weights of the layer. Each bit of a weight value is stored in a binary valued memory cell of the memory array and each bit of the input is applied as a binary input to a word line of the array for the multiplication of the input with the weight. To perform a multiply and accumulate operation, the results of the multiplications are accumulated by adders connected to sense amplifiers along the bit lines of the array. The adders can be configured to multiple levels of precision, so that the same structure can accommodate weights and activations of 8-bit, 4-bit, and 2-bit precision.

Multi-precision digital compute-in-memory deep neural network engine for flexible and energy efficient inferencing

An innovative low-bit-width device may include a first digital-to-analog converter (DAC), a second DAC, a plurality of non-volatile memory (NVM) weight arrays, one or more analog-to-digital converters (ADCs), and a neural circuit. The first DAC is configured to convert a digital input signal into an analog input signal. The second DAC is configured to convert a digital previous hidden state (PHS) signal into an analog PHS signal. NVM weight arrays are configured to compute vector matrix multiplication (VMM) arrays based on the analog input signal and the analog PHS signal. The NVM weight arrays are coupled to the first DAC and the second DAC. The one or more ADCs are coupled to the plurality of NVM weight arrays and are configured to convert the VMM arrays into digital VMM values. The neural circuit is configured to process the digital VMM values into a new hidden state.

Hardware accelerated discretized neural network

Certain aspects of the present disclosure provide a method for performing multimode inferencing, comprising: receiving machine learning model input data from a requestor; processing the machine learning model input data with a machine learning model using processing hardware at a first power level to generate first output data; selecting a second power level for the processing hardware based on comparing the first output data to a threshold value; processing the machine learning model input data with the machine learning model using the processing hardware at the second power level to generate second output data; and sending second output data to the requestor.

Variable power mode inferencing

Methods and systems for testing memory systems are disclosed. A refresh rate for a test system including a number of memory devices may be controlled based on estimated power scenario of a memory system design. In response to performance of a number of refresh operations on the memory devices and based on the refresh rate, one or more conditions of the test system may be monitored to generate estimated performance data for the memory system design.

Generating test data for a memory system design based on operation of a test system, and related methods, devices, and systems

Non-volatile memory structures for performing compute in memory inferencing for neural networks are presented. To improve performance, both in terms of speed and energy consumption, weight matrices are replaced with their singular value decomposition (SVD) and use of a low rank approximations (LRAs). The decomposition matrices can be stored in a single array, with the resultant LRA matrices requiring fewer weight values to be stored. The reduced sizes of the LRA matrices allow for inferencing to be performed more quickly and with less power. In a high performance and energy efficiency mode, a reduced rank for the SVD matrices stored on a memory die is determined and used to increase performance and reduce power needed for an inferencing operation.

Compute-in-memory deep neural network inference engine using low-rank approximation technique

Methods and apparatus are disclosed for implementing principal component analysis (PCA) within a non-volatile memory (NVM) die of solid state drive (SSD) to reduce the dimensionality of machine learning data before the data is transferred to other components of the SSD, such as to a data storage controller equipped with a machine learning engine. The machine learning data may include, for example, training images for training an image recognition system in which the SSD is installed. In some examples, the on-chip PCA components of the NVM die are configured as under-the-array or next-to-the-array components. In other examples, one or more arrays of the NVM die are configured as multiplication cores for performing PCA matrix multiplication. In still other aspects, multiple NVM dies are arranged in parallel, each with on-chip PCA components to permit parallel concurrent on-chip processing of machine learning data.

Non-volatile memory with on-chip principal component analysis for generating low dimensional outputs for machine learning

Techniques are presented for performing in-memory matrix multiplication operations for binary input, binary weight valued convolution neural network (CNN) inferencing. The weights of a filter are stored in pairs of memory cells of a storage class memory device, such as a ReRAM or phase change memory based devices. To reduce current consumption, the binary valued filters are transformed into ternary valued filters by taking sums and differences of binary valued filter pairs. The zero valued weights of the transformed filters are stored as a pair of high resistance state memory cells, reducing current consumption during convolution. The results of the in-memory multiplications are pair-wise combined to compensate for the filter transformations. To compensate for zero valued weights, a zero weight register stores the number of zero weights along each bit line and is used to initialize counter values for accumulating the multiplication operations.

Kernel transformation techniques to reduce power consumption of binary input, binary weight in-memory convolutional neural network inference engine

Use of a NAND array architecture to realize a binary neural network (BNN) allows for matrix multiplication and accumulation to be performed within the memory array. A unit synapse for storing a weight of a BNN is stored in a pair of series connected memory cells. A binary input is applied on a pair of word lines connected to the unit synapse to perform the multiplication of the input with the weight. The results of such multiplications are determined by a sense amplifier, with the results accumulated by a counter. The arrangement extends to ternary inputs to realize a ternary-binary network (TBN) by adding a circuit to detect 0 input values and adjust the accumulated count accordingly. The arrangement further extends to a ternary-ternary network (TTN) by allowing 0 weight values in a unit synapse, maintaining the number of 0 weights in a register, and adjusting the count accordingly.

Realization of neural networks with ternary inputs and ternary weights in NAND memory arrays

Techniques are presented for accelerating in-memory matrix multiplication operations for a convolution neural network (CNN) inference in which the weights of a filter are stored in the memory of a storage class memory device, such as a ReRAM or phase change memory based device. To improve performance for inference operations when filters exhibit sparsity, a zero column index and a zero row index are introduced to account for columns and rows having all zero weight values. These indices can be saved in a register on the memory device and when performing a column/row oriented matrix multiplication, if the zero row/column index indicates that the column/row contains all zero weights, the access of the corresponding bit/word line is skipped as the result will be zero regardless of the input.

Accelerating sparse matrix multiplication in storage class memory-based convolutional neural network inference

Systems and methods for reducing the impact of defects within a crossbar memory array when performing multiplication operations in which multiple control lines are concurrently selected are described. A group of memory cells within the crossbar memory array may be controlled by a local word line that is controlled by a local word line gating unit that may be configured to prevent the local word line from being biased to a selected word line voltage during an operation; the local word line may instead be set to a disabling voltage during the operation such that the memory cell currents through the group of memory cells are eliminated. If a defect has caused a short within one of the memory cells of the group of memory cells, then the local word line gating unit may be programmed to hold the local word line at the disabling voltage during multiplication operations.

Methods to tolerate programming and retention errors of crossbar memory arrays

Technology for reconfigurable input precision in-memory computing is disclosed herein. Reconfigurable input precision allows the bit resolution of input data to be changed to meet the requirements of in-memory computing operations. Voltage sources (that may include DACs) provide voltages that represent input data to memory cell nodes. The resolution of the voltage sources may be reconfigured to change the precision of the input data. In one parallel mode, the number of DACs in a DAC node is used to configure the resolution. In one serial mode, the number of cycles over which a DAC provides voltages is used to configure the resolution. The memory system may include relatively low resolution voltage sources, which avoids the need to have complex high resolution voltage sources (e.g., high resolution DACs). Lower resolution voltage sources can take up less area and/or use less power than higher resolution voltage sources.

Reconfigurable input precision in-memory computing

A non-volatile memory device includes an array of non-volatile memory cells that are configured to store weights of a neural network. Associated with the array is a data latch structure that includes a page buffer, which can store weights for a layer of the neural network that is read out of the array, and a transfer buffer, that can store inputs for the neural network. The memory device can perform multiply and accumulate operations between inputs and weight of the neural network within the latch structure, avoiding the need to transfer data out of the array and associated latch structure for portions of an inference operation. By using binary weights and inputs, multiplication can be performed by bit-wise XNOR operations. The results can then be summed and activation applied, all within the latch structure.

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San Jose, CA, United States of America

Won Ho Choi