Electronics and Telecommunications Research Institute

Won-Gu Kang

Sung-Weon Kang

Hyun-Kyu Yu

Sang-Won Kang

Dae-Yong Kim

Jin-Hyo Lee

Kyu-Hong Lee

Jong-Sun Lyu

Yeo-Whan Kim

A metal oxide semiconductor device with a self-aligned groove channel structure is disclosed comprising a substrate in which a first channel region of a first conductivity type and source and drain regions of a second conductivity type are formed, a first gate insulating layer formed on the first channel region, and a first gate electrode formed on the gate insulating layer, a second gate electrode having a self-aligned groove structure formed at both sides of the first gate electrode; a second gate insulating layer formed between the substrate and the second gate insulating layer; and a non-planar second channel region of the first conductivity type formed under the second gate insulating layer and doped with a different concentration of an impurity from the first channel region. The groove structure prevents an electric field produced in the vicinity of a drain from penetrating into the channel region to lessen a short channel effect. The length of an effective channel is increased by the groove structure, and also a junction depth of source/drain regions can be further increased by a depth of the groove in comparison with the conventional MOS device. The source/drain resistance is lowered, and reliability is increased due to lessening the effect of a junction spike of a metallization and/or an electro-migration.

Metal oxide semiconductor device with self-aligned groove channel and

There are disclosed a semiconductor device having electrical elements buried a SOI substrate and a manufacturing method thereof, the manufacturing method of the invention comprising the steps of: (a) forming a first isolating insulator layer at a seed wafer by using an isolation mask, depositing a second isolating insulator layer overlying the first isolating insulator layer and the seed wafer, and defining contact holes by using a contact mask to form contacts on the seed wafer; (b) depositing a first polysilicon layer on the second isolating insulator layer and the contacts and doping an impurity into the first polysilicon layer; (c) patterning the first polysilicon layer to define an electrical element, depositing an insulating layer around the electrical element, and forming a second polysilicon layer overlying the second isolating insulator layer and the insulating layer; (d) doping an impurity into the second polysilicon layer for connecting with a handling wafer, and polishing the second polysilicon layer thus doped to form a mirror surface; (e) depositing an insulating layer for connection on the handling wafer, and performing a thermal process to bond the handling wafer and the mirror surface through the insulating layer for connection; and (f) polishing the seed wafer until the first isolating insulator layer as a polishing stopper is exposed, to form the SOI substrate having an active region where a device is formed, by the invention the efficiency of chip area can be promoted.

Method of manufacturing a semiconductor device having buried elements

A bipolar DRAM comprises a switching transistor, a storage capacitor and a substrate. The switching transistor and the storage capacitor are vertically stacked with each other. The switching transistor is preferably an NPN bipolar transistor. The switching transistor preferably comprises P.sup.- base region, an N.sup.+ emitter region of the substrate, a N.sup.+ collector region, with a lower epitaxial layer between the N.sup.+ emitter region and P.sup.- base region, and an upper epitaxial layer between the P.sup.- base region and N.sup.+ collector region. The storage capacitor comprises a storage electrode formed on the N.sup.+ collector region, a dielectric layer and a plate electrode. The dielectric layer and the plate electrode are vertically and sequentially stacked on the storage electrode. A bit line is formed on the plate electrode, and a word line is formed on the side surface of the P.sup.+ base region.

Vertically stacked bipolar dynamic random access memory

Growing community of inventors

Daejeon, South Korea

Won-Gu Kang