Samsung Electronics Co., Ltd.

Won-Gil Han

Yong-Je Lee

Byong-Joo Kim

Seung-Weon Ha

Se-Jin Yoo

Jae-Heung Lee

Hong-Sub Joo

Sung-Il Cho

Min Seop Kim

Ho-Tae Jin

Yong Je Lee

Sangho An

Jae Heung Lee

Seungweon Ha

Yean-Sang You

Han-Ki Park

Seung-Lo Lee

Ho-Am Kim

Do-Hoon Lee

Se-Yeoul Park

In a method of manufacturing a semiconductor package, a first semiconductor device is arranged on a package substrate. An electrostatic discharge structure is formed on at least one ground substrate pad exposed from an upper surface of the package substrate. A plurality of second semiconductor devices is stacked on the package substrate and spaced apart from the first semiconductor device, the electrostatic discharge structure being interposed between the first semiconductor device and the plurality of second semiconductor devices. A molding member is formed on the package substrate to cover the first semiconductor device and the plurality of second semiconductor devices.

Semiconductor package

Method of manufacturing a semiconductor package

A semiconductor package includes a package substrate, at least one first semiconductor chip on the package substrate and having a first height as measured from the package substrate, at least one second semiconductor chip on the package substrate spaced apart from the first semiconductor chip and having a second height less than the first height as measured from the package substrate, at least one third semiconductor chip stacked on the first and second semiconductor chips, and at least one support structure between the at least one second semiconductor chip and the at least one third semiconductor chip configured to support the at least one third semiconductor chip.

Semiconductor package including multiple semiconductor chips and method of manufacturing the semiconductor package

A multi-chip package includes a package substrate including a first substrate pad, a first group of semiconductor chips stacked on the package substrate, each of the first group of the semiconductor chips including bonding pads, first stud bumps arranged on the bonding pads of the first group of the semiconductor chips except for a lowermost semiconductor chip in the first group, a first conductive wire downwardly extended from the bonding pad of the lowermost semiconductor chip in the first group and connected to the first substrate pad, and a second conductive wire upwardly extended from the bonding pad of the lowermost semiconductor chip in the first group and sequentially connected to the first stud bumps.

Method of manufacturing multi-chip package

A bonding wire includes a wire core including a silver-palladium alloy. A coating layer is disposed on a sidewall of the wire core. A palladium content of the silver-palladium alloy ranges from about 0.1 wt % to about 1.5 wt %.

Bonding wire having a silver alloy core, wire bonding method using the bonding wire, and electrical connection part of semiconductor device using the bonding wire

Multi-chip package and method of manufacturing the same

In a method of detecting faults of operation algorithms in a wire bonding machine, individual bond parameters with respect to each of the operation algorithms of the wire bonding machine can be set based on design data including information with respect to conductive wires connected between semiconductor chips of a semiconductor package. Actual conductive wires of an actual semiconductor package can be formed using the wire bonding machine into which the design data can be inputted. Actual data with respect to actual operation algorithms of the wire bonding machine, which can form the actual conductive wires, can be obtained. The actual data can be compared with the individual bond parameters to detect the faults of the operation algorithms of the wire bonding machine. Thus, forming an abnormal conductive wire by the wire bonding machine can be prevented beforehand.

Method of detecting faults of operation algorithms in a wire bonding machine and apparatus for performing the same

A multi-chip package may include a first semiconductor chip, a second semiconductor chip, a first stud bump, a first nail head bonding bump, a second stud bump, and a first conductive wire. The first semiconductor chip may have a first bonding pad. The second semiconductor chip may be stacked on the first semiconductor chip so the first bonding pad remains exposed. The second semiconductor chip may have a second bonding pad. The first stud bump may be formed on the first bonding pad. The first nail head bonding bump may be formed on the first stud bump, with one end of a first conductive wire formed between the two. The second stud bump may be formed on the second bonding pad, with another end of the first conductive wire formed between the two. An electrical connection test may be performed on each of the wire bonding processes.

A stacked semiconductor package and an electronic system, the stacked semiconductor package including a plurality of semiconductor chips, a set of the semiconductor chips being stacked such that an extension region of a top surface of each semiconductor chip of the set extends beyond an end of a semiconductor chip stacked thereon to form a plurality of extension regions; and a plurality of protection layers on the extension regions and on an uppermost semiconductor chip of the plurality of semiconductor chips.

Stacked semiconductor package and method of fabricating the same

Provided are a wire bonding apparatus and a method wire bonding and manufacturing a semiconductor device using the same. The wire bonding apparatus includes a heater block configured to support a stack including a chip mounting frame and a plurality of chips stacked on the chip mounting frame. The heater block is configured to supply heat to a first portion of the stack. The apparatus further includes a chip heating unit disposed at a different height from the heater block. The chip heating unit is configured to supply heat to a second portion of the stack at a different height from the first portion. The apparatus further includes a first temperature sensing unit positioned to be located at a first height and to determine a first temperature at the first portion of the stack, a second temperature sensing unit positioned to be located at a second height and to determine a second temperature at the second portion of the stack, and a temperature adjusting unit configured to compare the first temperature to the second temperature and to adjust the magnitude of the heat supplied by at least one of the heater block and the chip heating unit according to a result of the comparison.

Growing community of inventors

Cheongju-si, South Korea

Won-Gil Han