Electronics and Telecommunications Research Institute

Korea Telecom

Korea Telecommunication Authority

Won Chul Song

Kyung Soo Kim

Jong Kee Kwon

Chang Jun Oh

Ook Kim

Jong Ryul Lee

Mun Yang Park

Hee Bum Jung

Jong Dae Kim

Young Min Kim

Han Jin Cho

Jin Gun Koo

Gyu Hyung Cho

Sang H Chai

Hah Y Yoo

Jin I Hyun

Dong Youl Jeong

Q Sang Song

Provided is a CMOS exponential function generating circuit capable of compensating for the exponential function characteristic according to temperature variations. The exponential function generating circuit includes an voltage scaler scaling the value of an external gain control voltage signal, an exponential function generating unit generating exponential function current and voltage in response to a signal output from the voltage scaler, a reference voltage generator providing a reference voltage to the exponential function generating unit, and a temperature compensator compensating for the exponential function characteristic according to temperature variations.

CMOS exponential function generating circuit with temperature compensation technique

The present invention relates to a tuning circuit, more specifically to a tuning circuit for continuous-time filter capable of making exact the Gm value to minimize the variation of the cutoff frequency due to the variation of process in the Gm-C type of continuous-time filter. According to the invention, a frequency tuning circuit is provided which comprises integrating means for generating a signal discharging from a first reference voltage to a first predetermined value and a signal charging from a second reference voltage to a second predetermined value; offset sampling means for sampling the offset voltages of the Gm cells by receiving a current multiplied by the offset voltages from the Gm cells included in the integrating means and providing a feedback path between the output nodes and the input nodes of the included Gm cells; comparative signal generating means for generating a comparative signal by generating a reference signal by dividing a clock inputted from the external, receiving the signal discharging from the first reference voltage to the first predetermined value and the signal charging from the second reference voltage to the second predetermined value from the integrating means, and comparing the actual intersection and the target intersection of these signals; and control means for generating a control signal to regulate the Gm values of the integrating means and the offset sampling means by receiving the reference signal and the comparative signal from the comparative signal generating means and detecting the phase differences therebetween.

Low offset automatic frequency tuning circuits for continuous-time filter

A CMOS high frequency variable gain amplifier with maximum high frequency operation and wide variable gain characteristics that is formed from an amplifier having a plurality of variable gain amplifier cells connected in series for continuously enabling wide gain variation; and a control voltage generator for generating and outputting the control voltage of the variable gain amplifier cells. By using both the saturation region and the linear region of input differential transistors constituting the variable gain amplifier cells in order to obtain wide gain variation characteristics, it is possible for the variable gain amplifier to operate in the saturation region when the input signal is small to obtain a high gain and to operate in the linear region when the input signal is large to obtain minimum distortion and a low gain. Also, it is possible for the gain to have the characteristics in the form of an exponential function to the gain control voltage.

CMOS variable gain amplifier and control method therefor

Disclosed is a multiple feedback loop ring oscillator and delay cell with high oscillation voltage. It is an object of the present invention to implement a new ring oscillator for the VCO of a high speed PLL and a proper delay cell with a high speed and low noise. The apparatus is composed of multiple feedback loop ring oscillator that 4 delay cells which have the first main input stage, the second main input stage, the first subsidiary input stage, the second subsidiary input stage, the third subsidiary input stage, the forth subsidiary input stage, the first output stage and the second output stage is connected to the main loop and subsidiary loop. The present invention has advantages that it can be operated in high speed, it has a low power sensitivity, there is no power noise because there is no variation of a supply current and it can improve noise characteristics.

Multiple feedback loop ring oscillator and delay cell

There is disclosed a low frequency filter. A low frequency cutoff filter includes a filter circuit having a capacitor connected between an input terminal and an output terminal and an active resistor connected to the output terminal, having a very large resistance, and a bias circuit having a negative feedback to set a biasing voltage of the active resistor to a desired value, thereby implementing the cutoff filter within a semiconductor chip as one set with the capacitor having a small capacitance. A low frequency pass filter includes an active resistor having a very large resistance, means for setting a biasing voltage of the active resistor to a desired value, and a capacitor connected between the output terminal and the ground. Therefore, the low pass filter can be integrated-circuited using even small capacitor.

Low pass filter

A double mode modulator, particularly, for a portable telephone, which is adapted to realize both digital and analog modulations and have a low phase noise and a reduced locking time with a device readily integrated in an integrated circuit, including: a frequency synthesizer for synthesizing a particular frequency from an external reference clock signal; a digital modulator for performing a quadrature modulation for an output signal of the frequency synthesizer; and an analog modulator for performing a frequency modulation for the output signal of the frequency synthesizer.

Double mode modulator

The present invention relates to a high voltage driving circuit for preventing an transient current. The high voltage driving circuit including a non-overlap signal generator for generating the first and second non-overlap signals in response to the logic level signal, a satge for generating a first driving signal in response to the logic level signal and the first and second non-overlap signals, a pre-driving circuit which is driven in response to the first non-overlap signal and the first driving signal, and a complementary output circuit for controlling a current flowing toward the output terminal in response to the output signal of the pre-driving circuit and the second non-overlap signal.

High voltage driving circuit reducing a transient current

A tri-state logic circuit of a BiCMOS having a power saving characteristic, a strong noise durability, a desirable driving characteristic and switching charaacteristic is disclosed. The circuit comprises PMOS transistors M1,M5 and NMOS transistors M2,M3,M4,M6,M7,M8,M9 and bipolar transistors Q1,Q2 and a capacitor C1.

Growing community of inventors

Daejeon, South Korea

Won Chul Song