Samsung Electronics Co., Ltd.

Won-cheol Hong

Jae-Ho Kim

Young-woo Seo

Dug-dong Kang

Sun-cheol Hong

Min-wk Hwang

Hung-mo Yang

Won-taek Choi

Methods of forming integrated circuit memory devices, such as DRAM memory cells, include the steps of simultaneously forming storage electrode and bit line contact regions of first conductivity type in a semiconductor region of second conductivity type. The contact regions preferably receive a double dose of first conductivity type dopants. This double dose compensates for etching damage caused during processing and improves the memory cell's refresh characteristics. The preferred methods of forming DRAM memory cells include the steps of forming an electrically insulating layer on a face of a semiconductor substrate containing a region of second conductivity type therein (e.g., P-type) extending to the face, and then forming a word line (or segment thereof) on the electrically insulating layer, opposite the region of second conductivity type. Contact regions of first conductivity type for a storage electrode and bit line are then formed at the same time at adjacent opposing edges of the word lines by implanting dopants of first conductivity type into the region of second conductivity type using the word line as an implant mask. A storage electrode of a capacitor is then formed on (or coupled to) the storage electrode contact region adjacent a first edge of the word line and a bit line is also preferably formed on (or coupled to) the bit line contact region adjacent a second edge of the word line. The bit line contact region and storage electrode contact region preferably receive a double dose of first conductivity type dopants by performing a first ion implant step, forming sidewall spacers on the first and second edges of the word line and then performing a second ion implant step using the sidewall spacers as an implant mask.

Methods of forming integrated circuit memory devices having improved bit

Methods of forming semiconductor devices containing field oxide and channel-stop isolation regions therein include the steps of forming a plurality of first channel-stop isolation regions by implanting first conductivity type impurities at a first dose level into a face of a semiconductor substrate and then forming respective field oxide isolation regions at the locations where the first channel-stop isolation regions have been implanted. A conductive layer, which contacts active regions of the substrate and covers the field oxide isolation regions, is then patterned over the field oxide isolation regions to expose central portions of the upper surfaces of the field oxide isolation regions. The patterned conductive layer constitutes a landing pad layer which is preferably used as a mask during the formation of second channel-stop isolation regions in the substrate, by implanting first conductivity type impurities through the exposed upper surfaces of the field oxide isolation regions, into the centers of the first channel-stop isolation regions. During this step, the impurities are implanted at a higher dose and energy level so that the first and second channel-stop regions collectively form T-shaped channel-stop regions underneath respective field oxide isolation regions, when viewed in transverse cross-section. By reducing the concentration of the channel-stop impurities near the edges of the field oxide isolation regions and active regions, leakage currents can be reduced and refresh characteristics of memory devices can be improved by reducing the strength of parasitic electric fields in the substrate. However, by maintaining relatively high concentrations of the channel-stop impurities under the center of the field oxide isolation regions, electrical isolation of adjacent devices can be maintained at high levels.

Methods of forming integrated semiconductor devices having improved

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Kyungki-do, South Korea

Won-cheol Hong