Samsung Electronics Co., Ltd.

Won-chang Jung

Yun-sang Lee

Jung-Bae Lee

Hi-choon Lee

A semiconductor memory device and a read data skew control method thereof, in which a point of time when read data is output can he controlled using pad bonding in stack packages. The semiconductor memory device includes a bonding option pad and a delay control circuit that controls the point of time when data is output from an output buffer depending on logic states of a signal applied to the bonding option pad. Thus, when using the semiconductor memory device in stack packages, the read data skew generated as a result of a load on a bonding wire can be compensated by connecting the bonding option pad to ground voltage or a supply voltage.

Semiconductor memory device for stack package and read data skew control method thereof

Circuits and methods for refreshing memory banks in a DRAM are provided. A refresh circuit is provided in a DRAM having at least one memory bank and a plurality of word lines connected to memory locations in the memory bank. The word lines are subdivided into first and second groups of subword lines. The refresh circuit includes a delay circuit, a first driving circuit, and a second driving circuit. The delay circuit receives a refresh signal and outputs a delayed refresh signal a predetermined time delay later. The first driving circuit responds to the refresh signal by driving word lines in the first group of subword lines and the second driving circuit responds to the delayed refresh signal by driving word lines in the second group of subword lines.

DRAM partial refresh circuits and methods

Provided are a reset circuit of a data path using a clock enable signal, a reset method and a semiconductor memory device having the reset circuit. The reset circuit includes an external voltage detector and a second reset signal generator, in which the second reset signal is used to reset a block related to a data path of the semiconductor memory device. The external voltage detector detects the level of an external voltage and generates a first reset signal. The second reset signal generator performs a logical sum of an external signal, which is externally input, and the first reset signal, and generates a second reset signal. The first reset signal is used to reset blocks other than the blocks related to the data path. The external signal is a clock enable signal. In the soft reset, the blocks related to the data path are reset using the external signal which is applied at a certain level. Thus, data conflicts or ineffective data can be prevented in executing operations according to the read/write commands which are applied after the soft reset.

Data path reset circuit using clock enable signal, reset method, and semiconductor memory device including the data path reset circuit and adopting the reset method

An integrated circuit memory device includes an XY array of memory cell sub-blocks and row and column decoder circuitry that is electrically coupled to the array. The array includes first and second offset grids of sub-word line driver control circuits therein, with each of the sub-word line driver control circuits configured to selectively activate a pair of the memory cell sub-blocks in response to a respective pair of active row and column select signals. In order to improve power consumption requirements when switching back and fourth between normal and refresh modes of operation, the row and column decoder circuitry is configured to drive a selected one of a plurality of row select lines associated with the first grid with an asserted row select signal and a plurality of column select lines associated with the second grid with asserted column select signals during a write operation.

Integrated circuit memory devices having efficient column select signal generation during normal and refresh modes of operation and methods of operating same

A semiconductor memory device comprises a write column select line or read column select line for shielding a signal line. The semiconductor memory device may include a signal line, a read column select line, and a write column select line. The signal line may transmit an operation signal related to the operation of the semiconductor memory device. The read column select line may transmit a read column select signal, which may control transfer of a data signal of a bit line to a data line. The write column select line may transmit a write column select signal, which may control transfer of the data signal of the data line to the bit line. One of the read column select line and the write column select line to transmit a deactivated column select signal among the read column select signal and the write column select signal, may be maintained at a predetermined logic level and may shield the signal line.

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Kyungki-do, South Korea

Won-chang Jung