Samsung Electronics Co., Ltd.

Electronics and Telecommunications Research Institute

Korea Telecommunication Authority

Won-chan Kim

Chang-sik Yoo

Kee-wook Jung

Dae-yun Shim

Yeon-jae Jung

Young-Don Choi

Seung-wook Lee

Dong-yun Lee

Won-Chul Song

Sang-Hoon Chai

Joon-young Park

Chang-Sik Yu

Yi-do Koo

Hoon-Bock Lee

An output driver supplying constant output current regardless of output voltage changes. The output driver includes a current source for regulating changes in a voltage of an output terminal responsive to a reference signal, and an output current compensator that responds to the current source to supply constant current to the terminal. The current source includes a first MOS transistor having a drain coupled to the terminal and a gate to which the reference signal is input, and a second MOS transistor having a drain coupled to a source of the first MOS transistor, a gate to which data is input, and a source coupled to ground. The current source may be an open drain current source. The output current compensator includes a current compensator coupled to the terminal, and a sensing driver for sensing voltage changes of the terminal and driving the current compensator.

Output driver having output current compensation and method of compensating output current

A duty cycle correction circuit includes a duty cycle corrector and a detection circuit. The duty cycle corrector generates a first input signal having a second duty cycle with a higher degree of equivalence than the first duty cycle in response to a first detection signal and a first control signal having a first duty cycle. The detection circuit generates the first detection signal in response to the first input signal. The detection circuit includes a current source having first and second current sources and a bias circuit that is electrically coupled to the first and second current sources and controls a bias of the first and the second current sources responsive to the first input signal.

Duty cycle correction circuits that reduce distortion caused by mismatched transistor pairs

A ladder type clock network for reducing the skew of clock signals is provided. The clock network includes a buffer for buffering a clock signal, first delay units for delaying the output of the first buffer by a set time, second buffers connected to respective outputs of the first delay units, and second delay units connected to respective outputs of the second buffers. The first delay units and the second delay units consist essentially of the resistance and capacitance of lines through which the clock signal propagates. Accordingly, the skew of the internal clock signals is reduced, and internal clock signals having a stable duty with respect to variations in a semiconductor device manufacturing process, temperature, and power supply voltage, are generated.

Ladder type clock network for reducing skew of clock signals

An input buffer circuit for transforming pseudo differential input signals into full differential output signals wherein, the input buffer circuit includes a pull-up current source, two pull-down current sources, a differential input portion, and a positive feedback portion. The pull-up current source is formed of two PMOS transistors which are always in an &ldquo;on&rdquo; state, and provides an electric current. The two pull-down current sources are each formed of an NMOS transistor, which are always in an on state, and sink a pull-up electric current. The differential input portion is formed of two NMOS transistors, and receives an input signal and a reference signal, respectively. The positive feedback portion is formed of two NMOS transistors, and enlarges a voltage difference between two output terminals of the input circuit using positive feedback.

Input buffer circuit for transforming pseudo differential signals into full differential signals

A clock generating circuit for compensating for a delay difference using a closed loop analog synchronous mirror delay structure is provided. The clock generating circuit divides a delay clock signal and a reference clock signal to generate first and second divided signals, and synchronizes an internal clock signal with the reference clock signal using the first and the second divided signals, at the initial stage of an operation. After predetermined clock cycles, the clock generating circuit divides the internal clock signal to generate the first and the second divided signals. The quick synchronization of the internal clock signal with the reference clock obviates any error which may occur between the delay time of a mirror delay circuit and the delay time of an actual circuit.

Clock generating circuit for compensation of delay difference using closed loop analog synchronous mirror delay structure

A clock synchronization circuit is provided for synchronizing an external clock signal with an internal clock signal. The circuit is connected to a clock buffer adapted to output the internal clock signal. The circuit includes a first loop adapted to receive the external clock signal and output a plurality of reference clock signals having a predetermined phase difference therebetween. A second loop is adapted to delay the plurality of reference clock signals; select a signal from among the plurality of delayed reference clock signals; provide the selected signal to the clock buffer; detect a phase difference between the internal clock signal output from the clock buffer and the external clock signal; generate a plurality of control voltages to reduce the detected phase difference, and control a delay amount of each of the plurality of reference clock signals in response to the plurality of control voltages; so as to synchronize the internal clock signal with the external clock signal.

Clock synchronization circuit and semiconductor device having the same

Clock generating circuits include a clock buffer, a delay mirror circuit (DMC), a clock frequency divider circuit and a clock generator circuit. The clock buffer is responsive to an external clock signal EXTCLK and generates a buffered clock signal ICLK in response to the external clock signal EXTCLK. The buffered clock signal ICLK is delayed relative to the external clock signal EXTCLK by a fixed buffer delay time 'dtb'. The delay mirror circuit (DMC) is responsive to the buffered clock signal ICLK and generates a delayed clock signal IDCLK. The delayed clock signal IDCLK is delayed relative to the buffered clock signal ICLK by a fixed delay-mirror time 'dtot'. The clock frequency divider circuit is responsive to the buffered clock signal ICLK and the delayed clock signal IDCLK. The clock frequency divider circuit includes first and second divider devices that generate first and second divided clock signals VDIV1 and VDIV2, respectively. The clock generator circuit is responsive to VDIV1 and VDIV2 and includes a control signal generator, an analog pump signal generator and a driver circuit. Based on this configuration of the above-described circuits, only 2 clock periods are required before the rising edge of the internal clock signal INTCLK is in-sync and in-phase with the external clock signal EXTCLK.

Clock generating circuits that utilize analog pump signals to provide

A low power output buffer circuit for outputting an Emitter Coupled Logic(ECL) signal or Pseudo ECL(PECL) signal using a CMOS device is disclosed. The prior art differential output buffer circuit is comprised of two independent output buffer circuits and each output buffer circuit utilizes 50 ohms of the load resistors, having 20 mW of current to be applied to the circuit, which requires 100 mW of total consumptive power to operate the entire circuit. According to the present invention, a simplified output buffer circuit can be constructed by connecting 100 ohms of load resistors having a center tap to ground to two pads, which reduces half of the consumptive power as compared to that in the prior art circuit.

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Seoul, South Korea

Won-chan Kim