Samsung Electronics Co., Ltd.

Won-Bo Shim

Ji-Ho Cho

Sang-Wan Nam

Yong-Seok Kim

Byoung-taek Kim

Sun-gyung Hwang

Sang-Soo Park

Yoon Jin Kim

A program method of a nonvolatile memory device that performs a plurality of program loops is provided. At least one of the plurality of program loops includes dividing a channel of a selected cell string into a first side channel and a second side channel during a first interval and a second interval, turning off a string selection transistor of the selected cell string by applying a string select line voltage of a first level during the first interval, and boosting a first voltage of the first side channel and a second voltage of the second side channel, and turning on the string selection transistor by applying the string select line voltage of a second level different from the first level during the second interval, and performing a hot carrier injection (HCI) program operation on a selected memory cell corresponding to the first side channel or the second side channel.

Nonvolatile memory device and program method of the same

A nonvolatile memory device includes a memory cell region, a peripheral circuit region, a memory block in the memory cell region, a row decoder in the peripheral circuit region, and a control circuit in the peripheral circuit region. The memory cell region includes a first metal pad. The peripheral circuit region includes a second metal pad and is vertically connected to the memory cell region by the first metal pad and the second metal pad. The memory block includes memory cells stacked in a direction intersecting a substrate, and is divided into a plurality of sub-blocks configured to be erased independently. The row decoder selects the memory block by units of a sub-block. The control circuit receives a data erase command for a selected sub-block among the plurality of sub-blocks, performs a data read operation on at least one victim sub-block among the plurality of sub-blocks in response to the data erase command, selectively performs a soft program operation on the at least one victim sub-block based on a result of the data read operation, and performs a data erase operation on the selected sub-block after the data read operation is performed and the soft program operation is selectively performed.

Method of erasing data in nonvolatile memory device, nonvolatile memory device performing the same and memory system including the same

A method of operating a memory device includes performing a data read operation on at least one victim sub-block within a memory block containing a plurality of sub-blocks therein, in response to an erase command directed to a selected sub-block within the plurality of sub-blocks. Next, a soft program operation is performed on the at least one victim sub-block. This soft programming operation is then followed by an operation to erase the selected sub-block within the plurality of sub-blocks. This operation to erase the selected sub-block may include providing an erase voltage to a bulk region of a substrate on which the memory block extends, and the at least one victim sub-block may be disposed between the selected sub-block and the substrate.

A three-dimensional (3D) memory device having a plurality of vertical channel structures includes a first memory block, a second memory block, and a bit line. The first memory block includes first vertical channel structures extending in a vertical direction with respect to a surface of a substrate. The second memory block includes second vertical channel structures on the first vertical channel structures in the vertical direction and first and second string selection lines extending in a first horizontal direction and offset in the vertical direction. The bit line extends in the first horizontal direction between the first and second memory blocks and is shared by the first and second memory blocks. The second memory block may include first and second string selection transistors which are each connected to the bit line and the first string selection line and have different threshold voltages from each other.

Three-dimensional memory devices having plurality of vertical channel structures

A method of erasing a non-volatile memory device which includes a plurality of NAND strings is provided as follows. A first voltage is applied to each of word lines for a corresponding effective erasing execution time. An erase operation is performed on memory cells connected to each of the word lines for the corresponding effective erasing execution time. A second voltage is applied to each of at least some word lines among the word lines for a corresponding erasing-prohibited time after the corresponding effective erasing execution time elapses. A sum of the corresponding effective erasing execution time and the corresponding erasing-prohibited time for each of the at least some word lines is substantially equal to an erasure interval during which an erase operation is performed using the first voltage and the second voltage higher than the first voltage. The word lines are stacked on a substrate.

Memory device, memory system, method of operating the memory device, and method of operating the memory system

A method for operating a non-volatile memory device initially includes supplying an erase voltage to the memory cells. The memory cells are in cell strings in a three-dimensional structure. The method further includes performing a first read operation of the memory cells, performing a second read operation of the memory cells, and then performing a first erase verify operation based on results of the first and second read operations. The first erase verify operation may include performing a first exclusive-or (XOR) operation on the first and second read operation results.

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Seoul, South Korea

Won-Bo Shim