Infineon Technologies Ag

Infineon Technologies Dresden Gmbh

Infineon Technologies Austria Ag

Infineon Technologies Dresden Gmbh & Co . Kg

Wolfram Langheinrich

Robert Strenz

Mayk Roehrich

John Power

Florian Brandl

Robert Gruenberger

Danny Pak-Chum Shum

Danny Shum

Martin Stiftinger

Robert Wiesner

Peter Hagemeyer

Horst Theuss

Thoralf Kautzsch

Ronald Kakoschke

Bernhard Winkler

Dirk Meinhold

Mirko Vogt

Steffen Bieselt

Maik Stegemann

Heiko Froehlich

Claus Dahl

Bernhard Knott

Andre Roeth

Roland Meier

Ulrike Bewersdorff-Sarlette

Alfred Vater

Marco Haubold

Oliver Gehring

Sebastian Luber

A method of producing a quantum conveyor includes: forming a pair of screening gate electrodes in or on a semiconductor substrate and that extend between a first stationary quantum dot and a second stationary quantum dot, the pair of screening gate electrodes configured to delimit a channel of moveable quantum dots between the first stationary quantum dot and the second stationary quantum dot; forming, via a lithography process, a plurality of first planar transfer electrodes above the semiconductor substrate and that extend transverse to the channel of moveable quantum dots; and forming, via a self-aligned damascene process, a plurality of second planar transfer electrodes laterally interleaved with the first planar transfer electrodes, wherein the first planar transfer electrodes and the second planar transfer electrodes are configured to transfer quantum information between the first stationary quantum dot and the second stationary quantum dot through the channel of moveable quantum dots.

Quantum conveyor and methods of producing a quantum conveyor

A semiconductor device includes a first region; a second region that is peripheral to the first region; a substrate having a first surface and a second surface arranged opposite to the first surface; a stress-sensitive sensor disposed in the first region at the first surface of the substrate; a back end of line (BEOL) stack disposed on the first surface of the semiconductor chip that extends laterally from the MEMS element, in the first region, into the second region; a first cavity formed in the BEOL stack that exposes the sensitive area of the stress-sensitive sensor, wherein the first cavity extends entirely through the BEOL stack over the first region thereby exposing a sensitive area of the stress-sensitive sensor; and at least one stress-decoupling trench laterally spaced from the stress-sensitive sensor and laterally spaced from the first cavity with a portion of the BEOL stack interposed between.

Segmented stress decoupling via frontside trenching

A semiconductor device may include a stress decoupling structure to at least partially decouple a first region of the semiconductor device and a second region of the semiconductor device. The stress decoupling structure may include a set of trenches that are substantially perpendicular to a main surface of the semiconductor device. The first region may include a micro-electro-mechanical (MEMS) structure. The semiconductor device may include a sealing element to at least partially seal openings of the stress decoupling structure.

Stressed decoupled micro-electro-mechanical system sensor

A semiconductor device and a method of manufacturing the same are provided. The semiconductor device includes a semiconductor chip including a substrate having a first surface and a second surface arranged opposite to the first surface; at least one stress-decoupling trench that extends from the first surface into the substrate, where the at least one stress-decoupling trench extends partially into the substrate towards the second surface although not completely to the second surface; a microelectromechanical systems (MEMS) element, including a sensitive area, disposed at the first surface of the substrate and laterally spaced from the at least one stress-decoupling trench; and a stress-decoupling material that fills the at least one stress-decoupling trench and covers the sensitive area of the MEMS element.

Mechanical stress decoupling for microelectromechanical systems (MEMS) elements with gel-filling

A semiconductor device and a method of manufacturing the same are provided. The semiconductor device includes a semiconductor chip including a substrate having a first surface and a second surface arranged opposite to the first surface; a stress-sensitive sensor disposed at the first surface of the substrate, wherein the stress-sensitive sensor is sensitive to mechanical stress; a first pair of adjacent stress-decoupling trenches arranged laterally from a first lateral side of the stress-sensitive sensor, where each stress-decoupling trench of the first pair of adjacent stress-decoupling trenches extends partially from the first surface into the substrate towards the second surface although not completely to the second surface; and a first spring structure formed between the first pair of adjacent stress-decoupling trenches such that the first spring structure is arranged laterally from the stress-sensitive sensor and is configured to absorb external stress from an environment.

A method for processing a carrier accordance with various embodiments may include: forming a structure over the carrier, the structure including at least two adjacent structure elements arranged at a first distance between the same; depositing a spacer layer over the structure, wherein the spacer layer may be deposited having a thickness greater than half of the first distance, wherein the spacer layer may include electrically conductive spacer material; removing a portion of the spacer layer, wherein spacer material of the spacer layer may remain in a region between the at least two adjacent structure elements; and electrically contacting the remaining spacer material.

Chip and an electronic device

In one embodiment, a method of forming a semiconductor device is disclosed. A high-k dielectric is deposited of over a semiconductor body, and a portion of the high-k dielectric is wet etched an etchant selected from the group consisting of hot phos, piranha, and SC1.

Method of forming a non volatile memory device using wet etching

One or more embodiments are related to a semiconductor device, comprising: a high-K dielectric material; and a nitrogen-doped silicon material disposed over said high-k dielectric material.

Semiconductor device and method of making semiconductor device

Method for processing a carrier, method for fabricating a charge storage memory cell, method for processing a chip, and method for electrically contacting a spacer structure

In an embodiment of the invention, a memory cell arrangement includes a substrate and at least one memory cell including a charge storing memory cell structure and a select structure. The memory cell arrangement further includes a first doping well, a second doping well and a third doping well arranged within the substrate, wherein the charge storing memory cell structure is arranged in or above the first doping well, the first doping well is arranged within the second doping well, and the second doping well is arranged within the third doping well. The memory cell arrangement further includes a control circuit coupled with the memory cell and configured to control the memory cell such that the charge storing memory cell structure is programmed or erased by charging or discharging the charge storing memory cell structure via at least the first doping well.

Memory cell arrangement, method for controlling a memory cell, memory array and electronic device

The disclosed embodiments relate to a method for the production of a layer arrangement, a layer arrangement and a memory arrangement. According to one aspect at least one respectively laterally defined first layer sequence is embodied on a first surface area of a substrate and at least one respectively laterally defined second layer sequence is embodied on a second surface area of the substrate in order to produce a layer arrangement. A first side wall having a first thickness is respectively produced from a first electrically insulating material on at least one partial area of the side walls of the first and second layer sequences. A second side wall layer having a second thickness is respectively produced from a second electrically insulating material on at least one partial area of the first side wall layers and the second side wall layers are removed from the first layer sequences.

Method for fabricating a layer arrangement, layer arrangement and memory arrangement

A programmable read-only memory cell and method of operating the programmable read-only memory cell. In one embodiment, the programmable read-only memory cell comprises a floating gate arranged in a trench, an epitaxial channel layer formed on the floating gate, the channel layer connecting a source electrode to a drain electrode, and a selection gate arranged above the channel line.

Flash memory cell with buried floating gate and method for operating such a flash memory cell

A method for fabricating embedded nonvolatile semiconductor memory cells is described. The method includes forming a first insulating layer on a substrate having a high-voltage region, a memory region and a logic region. The first insulating layer is removed in the memory region, and a second insulating layer is formed. A charge-storing layer is formed and patterned along with a third insulating layer. The first to third insulating layers and also the charge-storing layer are removed in the logic region. A fourth insulating layer is formed and a conductive control layer is formed and patterned.

Growing community of inventors

Dresden, Germany

Wolfram Langheinrich