Infineon Technologies Ag

Wolfgang Stadler

Harald Gossner

Kai Esmark

Martin Wendel

Martin Streibl

Philipp Riess

Reinhold Gaertner

Bernd Goller

Richard Owen

Oliver Nagler

Xaver Guggenmos

Robert Bauer

Werner Ertle

Silke Bargstädt-Franke

Marin Streibl

Till Frohnmüller

Reinhard Greiderer

Olaf Schmeckebier

A semiconductor sensor device is electrically coupled to an object. An attachment member attaches the semiconductor sensor device to the object. The attachment member comprises a first conductive contact region and a second conductive contact region. An insulating portion is electrically isolates the semiconductor sensor device from the first conductive contact region and second conductive contact region.

Attachment member for semiconductor sensor device

A method of conducting an electrostatic discharge test on an integrated circuit is described. The method comprises configuring a test board assembly to emulate characteristics of a system in which the integrated circuit is to be used, coupling the integrated circuit to the test board assembly, and applying an electrostatic discharge test signal of system-level type to the test board assembly.

Electrostatic discharge test system and electrostatic discharge test method

A program-controlled arrangement for the identification of ESD and/or latch-up weak points in the design or in the concept of an integrated circuit comprises a pre-processor, which processes first data about the description of the integrated circuit, second data about already ESD-characterized circuit parts of the integrated circuit, and third data which contain information about ESD test standards. A simulator device is connected downstream of the pre-processor which has a simulator which, by using the fourth and fifth data generated by the pre-processor, performs an ESD simulation of the integrated circuit, which has a monitoring controller for controlling the ESD simulation sequence in the simulator. An analysis device is connected downstream of the simulator device, which performs an evaluation of the sixth data generated in the simulator device with regard to their physical validity and meaningfulness, and marks the simulation runs having physically relevant ESD failure events.

Identification of ESD and latch-up weak points in an integrated circuit

A circuit is described that protects an integrated circuit from electrostatic discharges or electrical over-stress. The circuit arrangement has first and second protective elements connected in series between a connection of the integrated circuit and a supply voltage. When electrostatic discharges or electrical over-stress occurs, current flows through the conductive path formed through the first and second protective elements. A current path that contains a circuit element limits current through the first protective element is connected in parallel with the first protective element. The first protective element has blocking behavior when no electrostatic discharges or electrical over-stress occurs, a limited current flows through the current path and the second protective element.

Circuit for protecting integrated circuits against electrostatic discharges

An integrated semiconductor structure has a substrate, a semiconductor element located on the substrate, a pad metal, metal layers located between the pad metal and the substrate, and insulation layers that separate the metal layers from one another. The pad metal extends over at least&#x2014;part of the semiconductor element. Below the surface of the pad metal, at least the top two metal layers include two or more adjacent interconnects.

Semiconductor structure integrated under a pad

To test the ESD resistance of a semiconductor component, for example of a NOS transistor, which can be used as a PSD protective element in a chip, a direct current characteristic of the semiconductor component is monitored and the ESD resistance of the respective semiconductor component is inferred depending on this. In particular, the direct current failure threshold of the semiconductor component at which an increased leakage current occurs in the non-conducting direction of the semiconductor component can be monitored in operation of the semiconductor component using an applied direct current and the ESD resistance of the semiconductor component inferred depending on a change in this direct current failure threshold.

Method and device for testing the ESD resistance of a semiconductor component

A method for determining an ESD/latch-up strength of an integrated circuit includes producing an integrated circuit and a test structure using the same fabrication process. Electrical parameters at the test structure are measured and characteristic values associated with the integrated circuit are derived from the measured parameter values, wherein the characteristic values characterize an ESD or latch-up characteristic curve associated with the integrated circuit. The method further includes testing whether the characteristic values in each case lie within a predetermined range assigned to them, wherein the ranges are chosen such that a desired ESD/latch-up strength is present if the characteristic values in each case lie within their range.

Method for determining an ESD/latch-up strength of an integrated circuit

The present invention creates an operating method for a semiconductor component having a substrate; having a conductive polysilicon strip which is applied to the substrate; having a first and a second electrical contact which are connected to the conductive polysilicon strip such that this forms an electrical resistance in between them; with the semiconductor component being operated reversibly in a current/voltage range in which it has a first differential resistance (Rdiff) up to a current limit value (It) corresponding to an upper voltage limit value (Vt) and, at current values greater than this, has a second differential resistance (Rdiff), which is less than the first differential resistance (Rdiff).

Operating method for a semiconductor component

The transistor has source and drain diffusion regions between which a gate electrode is disposed. In order to increase the sheet resistance of the source and/or drain diffusion regions, a plurality of strip-shaped insulating zones are provided, which penetrate through the corresponding diffusion region. The zones are oriented perpendicularly to the gate electrode and the end a given spacing distance from the gate electrode.

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Munich, Germany

Wolfgang Stadler