Qualcomm Incorporated

Apple Inc.

Lsi Logic Corporation

Transwitch Corporation

Nec Electronics America, Inc.

Nec Electronics Corporation

Lattice Semiconductor Corporation

Integrated Device Technology, Inc.

Wolfgang Roethig

Helena Deirdre O'Shea

Richard Dominic Wietfeldt

Lalan Jee Mishra

Michael G Frank

Chuan Wang

David J Maldonado

ZhenQi Chen

Attila Kovacs-Birkas

Ramakrishna Narayanaswami

Ashutosh Dikshit

Brijesh Tripathi

Anand Raghunathan

Chiew-Guan Tan

Christopher Kong Yee Chun

Wilson Jianbo Chen

Umesh Srikantiah

Craig M Okruhlica

Amir Bar-Niv

Ganesh Lakshminarayana

Arun Balakrishnan

Genady Veytsman

Scott Davenport

Jaeyoung Kwak

Lieu T Nguyen

Nader J Haddad

Various techniques are provided to implement programmable linear-feedback shift register (LFSR) circuits. In one example, the LFSR circuit includes state storage elements. Each state storage element is configured to store a state signal. The LFSR circuit further includes programmable logic stage circuits each configured to selectively receive an input signal and a set of state signals, determine an output signal based at least on the set of state signals, and provide the output signal. Each programmable logic stage circuit is connected to at least one other programmable logic stage circuit. The LFSR circuit further includes pipeline elements. Each pipeline element is configured to selectively connect at least two programmable logic stage circuits. The LFSR circuit further includes sets of latency balance elements. Related systems and methods are provided.

Programmable linear-feedback shift register systems and methods

Disclosed aspects relate to methods and apparatus for coexistent radio frequency (RF) systems in a wireless device. Control of a wireless device includes detecting when a turn on signal is issued to a first radio system, and then controlling the second radio system to either modify the operation of receiver circuitry in the second radio system to protect components within that system, or modify transmit circuitry to stop transmissions for protecting components within one radio system potentially affected by transmission from the other radio system in the wireless device. Disclosed also is monitoring of transmission states of the radio systems based on reading messages between the first and second radio systems and issuing a notification message based thereon such that one of the radio systems may suspend monitoring of a transmit channel for permission to transmit in order to reduce power consumption due to such monitoring of the channel.

Controlling coexistent radio systems in a wireless device

Systems, methods, and apparatus for data communication are provided. A method performed by a bus master includes terminating transmission of a first datagram by signaling a first bus park cycle on a serial bus, causing a driver to enter a high-impedance state, opening an interrupt window by providing a first edge in a clock signal transmitted on a second line of the serial bus, closing the interrupt window by providing a second edge in the clock signal, signaling a second bus park cycle on the serial bus, initiating an arbitration process when an interrupt was received on the first line of the serial bus while the interrupt window was open, and initiating a transmission of a second datagram when an interrupt was not received on the first line of the serial bus while the interrupt window was open.

Asynchronous interrupt with synchronous polling and inhibit options on an RFFE bus

Methods and apparatuses are described that facilitate data communication between a first slave device and a second slave device across a serial bus interface. In one configuration, a master device receives, from a first slave device, a request to send a masked-write datagram to a second slave device via a bus, wherein the masked-write datagram is addressed to a radio frequency front end (RFFE) register of the second slave device. The masked-write datagram includes a mask field identifying at least one bit to be changed in the RFFE register and a data field providing a value of the at least one bit to be changed in the RFFE register. The master device detects whether the first slave device is authorized to send the masked-write datagram to the second slave device and permits the first slave device to send the masked-write datagram to the second slave device if authorization is detected.

Radio frequency front end devices with masked write

A method, an apparatus, and a computer program product for data communication are provided. The method may include providing a plurality of data channels on a communications link, determining unused bandwidth as a difference between total bandwidth provided by the communications link and bandwidth used by the plurality of data channels, allocating the unused bandwidth to a virtual channel, scheduling the plurality of data channels and the virtual channel in accordance with a time-based multiplexing scheme, and disabling interface circuitry used to couple the transmitter to the communications link when the virtual channel is scheduled. Each of the plurality of data channels may be assigned to a source of data to be transmitted on the communications link.

Method for arbitration and adaptive power-cycling in a multi-channel network

A dither unit with a programmable kernel matrix in which each indexed location/entry may store one or more dither values. Each dither value in a respective entry of the kernel matrix may correspond to the number of bits that are truncated during dithering. During dithering of each pixel of an image, entries in the kernel matrix may be indexed according to the relative coordinates of the pixel within the image. A dither value for the pixel may be selected from the indexed entry based on the truncated least significant bits of the pixel component value. When the kernel matrix is storing more than one dither value per entry, the dither value may be selected based further on the number of truncated least significant bits. A dithered pixel component value may then be generated according to the dither value and the remaining most significant bits of the pixel component value.

Non-real-time dither using a programmable matrix

In an embodiment, a display apparatus includes multiple physical interface circuits (PHYs) couple to respective displays. In a mirror mode, the PHYs may operate as masters. A primary master PHY may control a synchronization interface to one or more secondary master PHYs. The synchronization interface may include a start of frame signal that the primary master PHY may generate to indicate the beginning of a new frame. The secondary master PHYs may be configured to generate internal start of frame signals while independently processing the same display data as the primary master. If the internally-generated start of frame and the received start of frame occur within a window of tolerance of each other, then the secondary masters may continue to process the display data stream independently. A secondary master that detects the start of frames occur outside of the window of tolerance may resynchronize.

Master synchronization for multiple displays

An adaptive equalizer for high-speed serial data comprises a programmable equalizer for equalizing an input serial data signal to generate an equalized serial data signal, wherein the equalization is based on an optimal equalization mode; a signal quality meter for computing an eye width indication based on the equalized serial data signal, wherein the eye width indication is an indicative of the quality of the equalized serial data signal; and a decision unit for determining the optimal equalization mode based on the eye width indication.

Adaptive equalizer for high-speed serial data

A system and method for transferring high-definition multimedia signals over four twisted-pairs. The system includes a multimedia source for transmitting multimedia data and source-to-sink management data to a multimedia sink over a first channel, a second channel and a third channel wherein the multimedia source is further being capable of transmitting a clock signal to the multimedia sink over a fourth channel; and a multimedia sink for transferring sink-to-source management data to the multimedia source over the fourth channel. The clock signal and the sink-to-source management data are simultaneously transmitted over the fourth channel. Each of the channels comprises a single twisted-pair, thereby the channels can bounded in a twisted pair type cable comprising at least one of: Category 5, Category 5e, Category 6, and Category 6e.

System and method for transferring high-definition multimedia signals over four twisted-pairs

A method for designing a video processor with a variable and programmable bitwidth parameter. The method comprises selecting logical operations having propagation delay that scales linearly with the bitwidth; determining a desired tradeoff curve; and grouping instances of a logic operation having same properties; for a single instance of each logic operation, matching an actual curve of the logic operation to the desired tradeoff curve, wherein the actual curve is determined by the propagation delay and bitwidth of the logic operation.

Method for constructing a variable bitwidth video processor

An auto-adaptive digital phase locked loop (DPLL) includes a phase detector comprising an edge detector having an input that receives an input clock, and an output that outputs a reference event generated from a reference edge of the input clock. The DPLL also includes a programmable first counter that counts down at the generated clock rate, the first counter having a first input that is programmed with an integer value M, a second input that receives the generated clock, and an output that outputs a counter state based on the generated clock and the integer value M. A first register has a first input that receives the reference event, a second input that receives the counter state, and an output that outputs a sample value N(t), wherein the register stores the counter state as the sampled value N(t) that represents a code for a phase between the reference event and the counter state.

Auto-adaptive digital phase-locked loop for large frequency multiplication factors

A method involves: accessing data representing an interconnect model, where the interconnect model includes a driving point node and is not a lumped capacitance model; calculating a value of an effective capacitance of the interconnect model to be inversely proportional to a voltage at the driving point node of the interconnect model; and storing the value of the effective capacitance. Such a method can be used to calculate effective capacitance of the interconnect model using analytical techniques.

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San Jose, CA, United States of America

Wolfgang Roethig