Siemens Aktiengesellschaft

Linde Aktiengesellschaft

Saudi Basic Industries Corporation

Wolfgang Peter Mueller

Marco Harff

Anina Woehl

Mohammed Hassan Al-Hazmi

Andreas Meiswinkel

Uwe Rosenthal

Normen Peulecke

Heinz Boelt

Abdullah Al-Qahtani

Bernd H Mueller

Lothar Risch

Shahid Azam

Anton Wellenhofer

Reinhard Tielert

Shehzada Khurram

Karl-Heinz Hofmann

Abduljelil Iliyas

Christoph Werner

Abdullah Alqahtani

Ewald Soutschek

Alfred Schuetz

Guenther Vorbach

Ewald Dotzauer

Hans-Jorg Zander

Karl-Heinz Kuesters

Gerd Enders

Andreas Meiswinkle

Alois Altendorfer

A catalyst composition including: (a) a chromium compound; (b) a ligand of the general structureRRP&#x2014;N(R)&#x2014;P(R)&#x2014;NRRor&#x2003;&#x2003;(A)RRP&#x2014;N(R)&#x2014;P(XR)Ror RRP&#x2014;N(R)&#x2014;P(XR), with X&#x2550;O or S,&#x2003;&#x2003;(B)wherein R, R, R, R, R, R, Rand Rare independently C-C-alkyl, C-C-aryl, C-C-cycloalkyl, aralkyl, alkylaryl, or trialkylsilyl, or any cyclic derivatives of (A) and (B), wherein at least one of the P or N atoms of the PNPN-unit or PNP-unit is a member of the ring system, the ring system being formed from one or more constituent compounds of structures (A) or (B) by substitution; and (c) an activator or co-catalyst; and a process for tri- and/or tetramerization.

Catalyst composition and process for oligomerization of ethylene

The present invention relates to a method for oligomerization of ethylene, comprising the steps:

Method for oligomerization of ethylene

A catalyst composition including: (a) a chromium compound; (b) a ligand of the general structure

A three-dimensional, one transistor cell arrangement for dynamic semiconductor memories utilizing a trench capacitor in the substrate, and provided with a switching field effect transistor including an insulated gate electrode connected to the source/drain zone, the bit line contact for the connection of the switching transistor being arranged to be self-adjusted on the drain region in the semiconductor substrate, and overlapping the gate electrode with insulating layers on all sides. It also overlaps the neighboring field oxide region. The insulation layer laying beneath the bit line and over the gate level is a triple layer composed of silicon oxide/silicon nitride/silicon oxide, and in the through hole etching which is carried out by specific etching steps, there exists a self-adjusted overlapping contact. By eliminating the imprecision caused by the lithography, the space requirement of a memory cell can be reduced by about 20%. The invention is particularly utilized in the manufacture of 4 megabit DRAMs.

Three-dimensional one-dimensional cell arrangement for dynamic

A voltage-stable sub-.mu.m-MOS transistor for VLSI circuits consist of a low-resistant silicon substrate of a first conductivity type with a high-resistant, thin, epitaxial layer of the first conductivity type situated thereon and on which a gate electrode consisting of polysilicon is disposed. Highly doped source/drain zones of the second conductivity type form a channel region of the first conductivity type. A doping substance concentration, rising in the direction of the substrate, is generated by means of double implantation, whereby the concentration maximum extends to behind the source/drain zones. A method for manufacturing same incorporates steps of forming the several layers, applying a mask, executing a double implantation in the channel region, and forming the gate electrode.

Voltage-stable sub-.mu.m MOS transistor for VLSI circuits

An integrated circuit for a dynamic semiconductor random access memory, constructed of complementary transistors, has memory cells connected to bit lines by way of individual selection transistors of a first channel type, the operation of which is controlled by word lines. The voltage on the word lines is controlled by a first switching transistor of a second channel type, controlled by the output of a decoder. The first switching transistor is connected between the word line and a selection voltage which alternates between two voltage values of different operational signs, and the gate of the first switching transistor is connected through a capacitor to the selection voltage and through a second switching transistor having its gate at reference potential, to the output of the decoder.

Integrated dynamic semiconductor memory with complementary circuitry and

The manufacture of n-channel and p-channel transistors in a CMOS process which involves employing gate spacer oxide layers for of reducing the under-diffusion of the implanted source-drain regions under the gate areas. The spacer oxide widths for the n-channel and the p-channel transistor are set differently so that both transistor types can be optimized independently of one another and without an additional expenditure for more masking steps. The method is employed for the manufacture of large scale integrated circuits for fast switching speeds.

Method for the manufacture of complementary MOS field effect transistors

A one-transistor memory cell comprises a semiconductor body which has a thin insulating layer on a boundary surface and a conductive layer on the thin insulating layer, the conductive layer representing that electrode of a storage capacitor that is connected to a selection field effect transistor. The selection field effect transistor is realized in a layer applied as a polycrystalline semiconductor layer and is then recrystallized. The memory cell provides the smallest possible semiconductor surface. This is achieved in that the recrystallized semiconductor layer is disposed above the conductive layer 3 and is separated therefrom by an intermediate insulating layer, whereby it extends in the lateral direction, at most, up to the edge of the semiconductor layer 3.

One-transistor memory cell for large scale integration dynamic

In a small PABX with a switching matrix that has electronic crosspoints, integrated selector components comprising multiplexers or demultiplexers in C-MOS technology are used for the switching matrix. By means of individual dialing connection points, which are determined by an appropriate control address supplied by a control computer unit, the individual subscriber lines are to be connected together in internal traffic, and the subscriber lines are to be connected with an exchange line in external traffic. The switching matrix is electrically separated from other operating units by repeating coils in the subscriber lines and in the exchange lines. Central units (tone receiver, tone generator) are connected through free dialing connection points of the multiplexers.

Circuit arrangement for a small PABX with a switching matrix that has

A RAM memory cell in double polysilicon technology having improved packing density is attained by insulating neighboring active memory regions under a first polysilicon plane by ion implantation to increase the substrate doping of the surface of the semiconductor body whereby field shield insulation regions are generated by a transistor in the off-state and the memory regions are rendered self-conducting by the ion implantation so that with a voltage at the polysilicon-1-electrode of 0 volts, the full operating voltage can be written into the memory capacitor.

Dynamic semiconductor memory cell with random access and method for its

The invention provides a method of manufacturing dynamic semiconductor memory cells having random access (RAM) in accordance with the double polysilicon gate technology, with which insulation of adjacent, active regions occurs by thick oxide regions, produced according to known LOCOS technology and with which, for increasing cell capacity, a boron and arsenic ion implantation is executed into the memory region with the use of a photoresist mask. In order to increase component density, the oxide thickness in the memory region/thick oxide transistor region is reduced in a multi-stage etching sequence, axially as well as laterally, so that a gain of about 25% in memory surface and a gain of more than 10 volts in blocking bias is achieved. The inventive method is particularly useful in the production of LSI Si.sup.2 gate RAM memories.

Method for producing dynamic semiconductor memory cells with random

A device for business machines, data and teleprinters and the like, for selectively adjusting the height of the ribbon guide thereof, at the printing station, into one of several operating positions and a visibility position in which the printing station of the machine is visible, in which the drive means for effecting movement of the ribbon guide comprises a stepping motor controlled by a drive circuit operative, in response to control criteria, to effect a positioning of the ribbon guide into either of two relatively extreme positions, or automatically into an intermediate position, in the absence of a selection of either such relatively extreme positions.

Device for adjusting the height of a ribbon guide

A guiding and threading device for automatic pitch-adapted threading of data carriers such as punched tape. The device includes a base member having a tape support surface thereon, a feed wheel carried by the base member with a portion projecting above the support surface, a first pivotable member carried by the base member having a guiding surface positioned above the support surface and a second pivotable member opposed to the first pivotable member and having a guiding surface positioned above the support surface, the guide surfaces forming a tape receiving channel between the pivotable members and the support surface when the pivotable members are at an open position. The guide surface of the first pivotable member urges the tape into contact with the feed wheel when in a closed position. The second pivotable member is when the with means engaging the first pivotable member limiting movement of the first pivotable member with respect to the second pivotable member to provide a substantially continuous guide surface whenthe pivotable members are in the open position.

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Munich, Germany

Wolfgang Peter Mueller