Infineon Technologies Ag

Wolfgang Nikutta

Dominique Savignac

Michael Kund

Thomas Von Der Ropp

Gunther Kuchinke

Jan Ten Br&ouml;ke

Rudolph Walter

Hartmut Schmokel

A memory apparatus includes a memory module array having several memory modules. Each memory module has a synchronization connection for receiving a synchronization signal for synchronizing the memory module relative to the other memory modules in the memory module array. This enables combining data bursts read from the memory modules into a data stream.

Array of synchronized memory modules

A circuit configuration has a calibration circuit, which is connected to terminals for two digital signals and has outputs for two digital output signals which are each derived from one of the digital signals. The calibration circuit effects temporal control of a switching edge of one of the output signals using a control value. A comparison circuit generates a comparison signal which indicates that one of the output signals has a switching edge first relative to the other output signal. The calibration circuit has a control input, through which the control value, which is stored in a storage circuit, can be set using the state of the comparison signal of the comparison circuit. The circuit configuration makes it possible to compensate undesirable propagation time differences between the digital signals.

Circuit configuration for receiving at least two digital signals

A method and a circuit configuration for a dynamic semiconductor memory are described in which, in order to reduce the parasitic coupling effects between two adjacent bit lines, in particular between a read line and a reference line, the adjacent line is put at a predetermined potential during the read operation. As a result, the read signal, which is very small in the worst-case scenario, is not adversely influenced by the coupling capacitance, since the inactive adjacent line acts as capacitive shielding. Advantageously, the read signals of the various active bit lines cannot mutually influence one another. A further refinement of the invention provides for the potential to be kept at the magnitude of the precharge state.

Method and circuit configuration for a memory for reducing parasitic coupling capacitances

A monolithically integrated test circuit for testing a digital semiconductor circuit configuration that is formed on the same semiconductor chip and has a large number of elements to be tested. The test circuit has a test data pattern register for temporary storage of a test data pattern, a read and write circuit for writing and reading the data in the test data pattern register to and from the elements to be tested, and a comparison circuit. The comparison circuit tests for any difference between the data written to and read from the elements to be tested. The test circuit has a pattern variation circuit, which can be activated by an activation signal and varies the test data pattern from the test data pattern register before writing into the elements to be tested.

Test circuit for testing a digital semiconductor circuit configuration

An apparatus for function testing of electronic circuits includes a tester array having a terminal. A test circuit has at least two resistor elements, a common circuit node connected to the resistor elements for connection to the terminal of the tester array, and terminals of the resistor elements each being remote from the circuit node for connection to a respective output of an electronic circuit to be tested. A testing method for function testing of electronic circuits with such an apparatus includes placing the electronic circuit into a state in which signals are present at an output of the electronic circuit to be tested. The electronic circuit is function tested with respect to a resultant signal being established at the common circuit node.

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Munich, Germany

Wolfgang Nikutta