Raytheon Company

Wolfgang M Feist

Hermann Statz

Amos Picker

A method of forming a bipolar transistor. A base region is implanted into an epitaxial layer. An emitter and collector contact regions are formed of doped polysilicon on the epitaxial layer, the emitter being formed over the base region. The implant is below the surface of the epitaxial layer in all regions not covered by the collector region. Low resistance silicide contacts, such as titanium or cobalt, are formed on the structure in a self-aligned fashion. This method is well suited for forming BJTs as part of BiCMOS circuits.

Method of forming bipolar transistor having closely spaced device regions

A method of forming a bipolar transistor comprising the steps of forming a base region in a semiconductor structure and disposing an emitter region on a surface of a first portion of the base region, the emitter region having upper and side surfaces. An active base region is formed in the first portion of the base region and an inactive base region is formed in a second portion of the base region adjacent to the first portion and the side surface of the emitter region. A layer of insulating material is formed over a surface of the inactive base region and over the upper and side surfaces of the emitter region. Portions of such layer are selectively removed to expose the upper surface of the emitter region and a portion of the surface of the inactive base region, and to maintain a region of insulating material between the exposed surface portion of the inactive base region and the side surface of the emitter region. Silicide contacts are formed on the exposed surface portion of the inactive base region and the exposed upper surface of the emitter region, with the insulating material region insulating such contacts from each other. With such arrangement, the spacing between the base and emitter contacts may be substantially reduced, such as to the width of the insulating material region, thereby reducing the size (i.e. width), base-to-emitter resistance, base contact resistance and base-to-emitter and base-to-collector capacitance of the bipolar transistor.

Method of forming a bipolar transistor having closely spaced device

A semiconductor structure is provided by forming an isolation region in a portion of a semiconductor layer, forming a doped region in the semiconductor layer adjacent the isolation region, such doped region having a conductivity type opposite the conductivity type of the semiconductor layer, selectively masking a surface of the semiconductor layer exposing a portion of the doped region adjacent to the isolation region, and selectively etching the exposed portions of the adjacent doped region forming a depression having converging side walls separated from the isolation region by portions of the doped region. The semiconductor layer is an epitaxial layer providing the collector region of a transistor. The bottom portion of the depression is lightly doped to provide an active base region for the transistor. The active base region is electrically connected to the base contact through the more heavily doped region formed in the semiconductor layer. A doped polycrystalline silicon layer is formed over the bottom portion of the depression in contact with the active base region to provide an emitter contact for the transistor.

Semiconductor structure and manufacturing method

A method for forming isolation regions in a semiconductor structure is provided. A mask comprising an upper and a lower layer of different materials is provided over the surface of the structure. A window is formed in the upper layer over the portions of the structure wherein the isolation regions are to be provided. Using the window in the upper layer as a mask, a larger window is formed in the lower layer by bringing a chemical etchant which etches only the lower layer into contact with the portions of the lower layer exposed by the window in the upper layer. The larger window formed in the lower layer is used as an etching mask to form an isolation groove, or depression, in the underlying semiconductor structure. The upper layer having the smaller window is used as an ion implantation mask for implanting particles into the bottom portion of the groove while masking the side portions of the grooves from the ions. With such method, lateral oxidation regions having self-registered anti-inversion regions which are located under the bottoms of the isolation regions and are spaced from the peripheries of the isolation regions by uniform, predetermined distances are obtained.

Method of forming isolated device regions by selective successive

A field effect device having a gate over a portion of a surface of a semiconductor disposed between a source region and a drain region and including a buried doped region having a conductivity type opposite the conductivity type of the semiconductor formed in the semiconductor under, and spaced from such portion of the surface of the semiconductor. The buried doped region is electrically connected to the gate electrode. With such arrangement a field effect device is formed with a connecting channel having a shallow depth in the semiconductor between the gate and the buried doped layer. A method for fabricating field effect devices is also disclosed, such method including the step of forming a pair of masking surfaces of insulating material on the surface of the semiconductor. An ion implantation masking layer is formed between the pair of masking surfaces to enable the selective implantation of particles in the semiconductor to establish the source and drain regions. With such method a single level of masking is used to define the source, drain and gate regions of the device.

Semiconductor devices and manufacturing methods

A semiconductor structure wherein a masking layer is formed to cover a portion of a surface of a semiconductor. A first doped region is formed in a portion of the semiconductor exposed by the masking layer. A chemical etchant is brought into contact with the masking layer, reducing the area of the masking layer covering the semiconductor exposing a second, different portion of the semiconductor contiguous to the first exposed portion of the semicoductor. Particles capable of establishing a doped region in the semiconductor layer are introduced into the second, different exposed portion of the semiconductor to form a second doped region in the semiconductor contiguous to the first doped region, such chemically etched masking layer inhibiting such particles from becoming introduced into the portion of the semiconductor disposed beneath the chemically etched masking layer. With such methods a self-aligned gate region may be formed in a field effect device having small channel lengths.

Method of making self-aligned gate MOS device having small channel

Method of forming closely spaced device regions utilizing selective

A two-phase buried-channel charge coupled device wherein a doped layer of first type conductivity is formed with a predetermined doping concentration under a surface of a semiconductor body of second type conductivity. A first plurality of electrodes is formed in spaced relationship on the surface over the doped layer. Particles generating the first type conductivity are ion implanted into regions of the doped layer between the first plurality of electrodes, increasing the doping concentration of the portion of the doped layer disposed beneath such spaced regions. A second plurality of electrodes is formed over the increased concentration portions of the doped layer. The first plurality of electrodes provides the transfer gates of the device and the second plurality of electrodes provides the storage gates for the device.

Charge coupled device

Semiconductor integrated circuit structures and manufacturing methods wherein isolation grooves are etched into a semiconductor body by first bringing an anisotropic etchant in contact with portions of the surface of the body which are exposed by windows formed in an etch-resistant mask to form grooves with side walls which intersect the surface at acute angles. Next, an isotropic etchant is brought in contact with the walls of the etched grooves to remove portions of the body which are underneath the etch-resistant mask such that the mask extends over the side walls of the resulting grooves, the bottom walls of such grooves are disposed under the windows and the side walls maintain acute angle intersection with the surface. Junction isolation regions are formed by ion implanting particles into the bottom walls of the grooves, the mask shielding the side walls from such particles. This self-aligning process accurately controls the placement of the junction isolation regions and thereby reduces the depth required for the grooves in providing dielectric isolation. Because the grooves have side walls which intersect the surface at acute angles, and because the grooves are relatively shallow because of the addition of accurately placed junction isolation regions, subsequent metallization processing is more readily controllable.

Method for manufacturing semiconductor structures by anisotropic and

Semiconductor integrated circuit structures and manufacturing methods wherein isolation grooves are etched into a semiconductor body by first bringing an anisotropic etchant in contact with portions of the surface of the body which are exposed by windows formed in an etch-resistant mask to form grooves with side walls which intersect the surface at acute angles. Next, an isotropic etchant is brought in contact with the walls of the etched grooves to remove portions of the body which are underneath the etch-resistant mask such that the mask extends over the side walls of the resulting grooves, the bottom walls of such grooves are disposed under the windows and the side walls maintain acute angle intersection with the surface. Junction isolation regions are formed by ion implanting particles into the bottom walls of the grooves, the maks shielding the side walls from such particles. This self-aligning process accurately controls the placement of the junction isolation regions and thereby reduces the depth required for the grooves in providing dielectric isolation. Because the grooves have side walls which intersect the surface at acute angles, and because the grooves are relatively shallow because of the addition of accurately placed junction isolation regions, subsequent metallization processing is more readily controllable.

Semiconductor structures and methods for manufacturing such structures

A display system having a cathode ray tube signal generator in which a solid state junction target utilizes a layer of semiconductor material and a layer of dielectric material to form a junction. The signal generator may be of the monoscope type in which portions of the target are masked or it may be of the photosensitive type in which an image is projected onto the target. A signal derived from the signal generator is displayed on a second cathode ray tube.

Semiconductor heterojunction television imaging tube

A semiconductor structure having a surface insulating layer formed as a grid with charges implanted in the insulating material to prevent inversion and, hence, channeling between adjacent semiconductor regions, preferably for use in a non-blooming vidicon. The method of manufacturing such a structure uses ion implantation to create immobile positive charges in a grid pattern in an insulating layer in regions spaced from the interface between the insulating layer and the semiconductor body. The insulating layer is of sufficient thickness that substantially all of the charge sites in the insulating layer are separated from the outer surface of the insulator by a sufficient distance to effectively prevent a negative electric field from reaching into the silicon.

Semiconductor devices having surface state control

A semiconductor structure having a surface insulating layer formed as a grid with charges implanted in the insulating material to prevent inversion and, hence, channeling between adjacent semiconductor regions, preferably for use in a nonblooming vidicon. The method of manufacturing such a structure uses ion implantation to create immobile positive charges in a grid pattern in an insulating layer in regions spaced from the interface between the insulating layer and the semiconductor body. The insulating layer is of sufficient thickness that substantially all of the charge sites in the insulating layer are separated from the outer surface of the insulator by a sufficient distance to effectively prevent a negative electric field from reaching into the silicon.

Semiconductor with surface insulator having immobile charges

A membrane type dielectric storage target formed from a thin refractory dielectric film is stretched to form at least a one-sided surface, a first surface portion contacting a conductive wire mesh, a second surface portion having areas coated with conductive material imaging the mesh of the first surface portion. The method contemplates forming the conductive image on the second surface portion by photo-resist, decoration, and breakdown techniques.

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Burlington, MA, United States of America

Wolfgang M Feist