Infineon Technologies Ag

Wolfgang Leiberg

Axel Brintzinger

Octavio Trovarelli

Matthias Lehr

David Wallis

Structures for signal distribution are produced by applying a metallic seed layer over a semiconductor body. An insulating layer is applied over the metallic seed layer and openings in the insulating layer are produced by photolithographic patterning of the insulating layer. Each opening in the insulating layer is trapezoidal in cross section such that an upper portion of the insulating layer is wider than a lower portion of the insulating layer. A conductor is selectively formed over exposed portions of the metallic seed layer. After selectively forming the conductor, the insulating layer is anisotropically etched such that portions of the insulating layer abutting sidewalls of the conductor remain. Alternatively, a second insulating layer can be formed and anisotropically etched.

Process for producing layer structures for signal distribution

An arrangement for protecting fuses/anti-fuses on chips which serve to activate redundant circuits or chip functions includes a passivation layer (e.g., hard passivation) arranged on a fully processed chip with the exception of metal contacts of a metallization level and the fuses. The chip is provided with a redistribution layer that is electrically contact-connected to the metallization level, and to a process for protecting such fuses/anti-fuses. The invention is now based on the object of ensuring sufficient protection of fuses/anti-fuses on integrated circuits. This is achieved by virtue of the fact that a dielectric (), which covers at least the region of the fuses/anti-fuses () and to which the redistribution layer () comprising the combination of materials Cu/Ni/Au is applied, is arranged on the passivation layer ().

Arrangement and process for protecting fuses/anti-fuses

The invention, which relates to a method for fabricating metallic interconnects with copper-nickel-gold layer construction on electronic components, is based on the object of specifying a method by means of which it is possible to fabricate such metallic interconnects on different electronic components cost-effectively by means of the known and tried and tested methods which have a comprehensive corrosion protection. According to the invention, the object is achieved by virtue of the fact that the interconnects are embodied such that they are completely encapsulated by being deposited in a manner buried in a patterned dielectric layer in the lower region and being covered in the upper region by a nickel-gold layer adjoining the lower encapsulation without any gaps.

Method for fabricating metallic interconnects on electronic components

A method for fabricating a wiring plane with antifuses is described. During the fabrication of the wiring plane on a semiconductor chip with the antifuses, provision is made of a buried antireflection layer in a dielectric layer. In the dielectric layer contact holes are formed, as a result of which only one etching step has to be carried out for the photolithography for forming interconnect trenches above the contact holes.

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Dresden, Germany

Wolfgang Leiberg