Infineon Technologies Ag

Infineon Technologies Austria Ag

Infineon Technologies Dresden Gmbh & Co . Kg

Wolfgang Jantscher

Ralf Siemieniec

David Kammerlander

Hans-Joachim Schulze

Hans Weber

Franz Hirler

Werner Schustereder

Joachim Weyers

Andreas Riegler

Manfred Pippan

Roland Rupp

Armin Willmeroth

Maik Stegemann

Waqas Mumtaz Syed

Yann Ruet

Oliver Blank

Helmut Strack

Dethard Peters

Ravi Keshav Joshi

Juergen Steinbrenner

Stefan Gamerith

Petra Fischer

Alexander Binter

Kurt Pekoll

A silicon carbide device includes a silicon carbide body with a trench gate structure that extends from a first surface into the silicon carbide body. A body region is in contact with an active sidewall of the trench gate structure. A source region is in contact with the active sidewall and located between the body region and the first surface. The body region includes a first body portion directly below the source region and distant from the active sidewall. In at least one horizontal plane parallel to the first surface, a dopant concentration in the first body portion is at least 150% of a reference dopant concentration in the body region at the active sidewall and a horizontal extension of the first body portion is at least 20% of a total horizontal extension of the body region.

Silicon carbide device with trench gate structure

In an example, for manufacturing a semiconductor device, first dopants are implanted through a first surface section of a first surface of a silicon carbide body. A trench is formed that extends from the first surface into the silicon carbide body. The trench includes a first sidewall surface and an opposite second sidewall surface. A spacer mask is formed. The spacer mask covers at least the first sidewall surface. Second dopants are implanted through a portion of a bottom surface of the trench exposed by the spacer mask. The first dopants and the second dopants have a same conductivity type. The first dopants and the second dopants are activated. The first dopants form a doped top shielding region adjoining the second sidewall surface. The second dopants form a doped buried shielding region adjoining the bottom surface.

Semiconductor device including trench gate structure and buried shielding region and method of manufacturing

A transistor cell includes a gate electrode and a source region of a first conductivity type. A drain/drift region is formed in a silicon carbide body. A buried region of the second conductivity type and the drain/drift region form a pn junction. The buried region and a well region form a unipolar junction. A mean net dopant density Nof the buried region is higher than a mean net dopant density Nof the well region. A first clamp region of the first conductivity type extends into the well region. A first low-resistive ohmic path electrically connects the first clamp region and the gate electrode. A second clamp region of the first conductivity type extends into the well region. A second low-resistive ohmic path electrically connects the second clamp region and the source region.

Silicon carbide device with transistor cell and clamp regions in a well region

A silicon carbide device includes a transistor cell with a source region and a gate electrode. The source region is formed in a silicon carbide body and has a first conductivity type. A first low-resistive ohmic path electrically connects the source region and a doped region of a second conductivity type. The doped region and a floating well of the first conductivity type form a pn junction. A first clamp region having the second conductivity type extends into the floating well. A second low-resistive ohmic path electrically connects the first clamp region and the gate electrode.

Silicon carbide device with transistor cell and clamp region

A MOSFET includes a semiconductor body having a first side, a drift region, a body region forming a first pn-junction with the drift region, a source region forming a second pn-junction with the body region, in a vertical cross-section, a dielectric structure on the first side and having an upper side; a first gate electrode, a second gate electrode, a contact trench between the first and second gate electrodes, extending through the dielectric structure to the source region, in a horizontal direction a width of the contact trench has, in a first plane, a first value, and, in a second plane, a second value which is at most about 2.5 times the first value, and a first contact structure arranged on the dielectric structure having a through contact portion arranged in the contact trench, and in Ohmic contact with the source region.

Methods for manufacturing a MOSFET

A method for forming a superjunction transistor device includes: forming a plurality of semiconductor layers one on top of the other; implanting dopant atoms of a first doping type into each semiconductor layer to form first implanted regions in each semiconductor layer; implanting dopant atoms of a second doping type into each semiconductor layer to form second implanted regions in each semiconductor layer. Each of implanting the dopant atoms of the first and second doping types into each semiconductor layer includes forming a respective implantation mask on a respective surface of each semiconductor layer, and at least one of forming the first implanted regions and the second implanted regions in at least one of the semiconductor layers includes a tilted implantation process which uses an implantation vector that is tilted by a tilt angle relative to a normal of the respective horizontal surface of the respective semiconductor layer.

Method for producing a transistor device having a superjunction structure

Silicon carbide device with trench gate structure and method of manufacturing

Method for forming a superjunction transistor device

A method for manufacturing a MOSFET semiconductor device includes providing a wafer including a semiconductor body having a first side, a first semiconductor region adjacent to the first side, a second semiconductor region adjacent to the first side and forming a first pn-junction with the first semiconductor region, and a third semiconductor region adjacent to the first side and forming a second pn-junction with the second semiconductor region, a first dielectric layer arranged on the first side, a gate electrode embedded in the first dielectric layer, and a second dielectric layer arranged on the first dielectric layer. Next to the gate electrode, a trench is formed through the first dielectric layer and the second dielectric layer. At a side wall of the trench, a dielectric spacer is formed. The trench is extended into the semiconductor body to form a contact trench.

A method of producing a semiconductor device includes providing a semiconductor body including a semiconductor body material having a dopant diffusion coefficient that is smaller than the corresponding dopant diffusion coefficient of silicon. At least one first semiconductor region doped with dopants of a first conductivity type is produced in the semiconductor body, including by applying a first implantation of first implantation ions. At least one second semiconductor region adjacent to the at least one first semiconductor region and doped with dopants of a second conductivity type complementary to the first conductivity type is produced in the semiconductor body, including by applying a second implantation of second implantation ions.

SiC-based superjunction semiconductor device

Disclosed is a method. The method includes implanting recombination center particles into a semiconductor body via at least one contact hole in an insulation layer formed on top of the semiconductor body, forming a contact electrode electrically connected to the semiconductor body in the at least one contact hole, and annealing the semiconductor body to diffuse the recombination center particles in the semiconductor body. Forming the contact electrode includes forming a barrier layer on sections of the semiconductor body uncovered in the at least one contact hole, wherein the barrier layer is configured to inhibit the recombination center particles from diffusing out of the semiconductor body.

Forming recombination centers in a semiconductor device

A method of manufacturing semiconductor devices in a semiconductor wafer comprises forming charge compensation device structures in the semiconductor wafer. An electric characteristic related to the charge compensation device structures is measured. At least one of proton irradiation and annealing parameters are adjusted based on the measured electric characteristic. The semiconductor wafer is irradiated with protons and annealed based on the at least one of the adjusted proton irradiation and annealing parameters. Laser beam irradiation parameters are adjusted with respect to different positions on the semiconductor wafer based on the measured electric characteristic. The semiconductor wafer is irradiated with a photon beam at the different positions on the wafer based on the photon beam irradiation parameters.

Semiconductor wafer and method of manufacturing semiconductor devices in a semiconductor wafer

A semiconductor device includes a semiconductor body having a semiconductor body material with a dopant diffusion coefficient that is smaller than the corresponding dopant diffusion coefficient of silicon, at least one first semiconductor region doped with dopants of a first conductivity type and having a columnar shape that extends into the semiconductor body along an extension direction, wherein a respective width of the at least one first semiconductor region continuously increases along the extension direction; and at least one second semiconductor region included in the semiconductor body. The at least one second semiconductor region is arranged adjacent to the at least one first semiconductor region, and is doped with dopants of a second conductivity type complementary to the first conductivity type.

A semiconductor device includes a semiconductor body with transistor cells arranged in an active area and absent in an edge area between the active area and a side surface. A field dielectric adjoins a first surface of the semiconductor body and separates, in the edge area, a conductive structure connected to gate electrodes of the transistor cells from the semiconductor body. The field dielectric includes a transition from a first vertical extension to a second, greater vertical extension. The transition is in the vertical projection of a non-depletable extension zone in the semiconductor body, wherein the non-depletable extension zone has a conductivity type of body/anode zones of the transistor cells and is electrically connected to at least one of the body/anode zones.

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Villach, Austria

Wolfgang Jantscher