Infineon Technologies Ag

Siemens Aktiengesellschaft

Qimonda Ag

Infineon Technologies LLC

Wolfgang Hönlein

Franz Kreupl

Franz Hofmann

Thomas Schulz

Michael Specht

Erhard Landgraf

Thomas Peter Haneder

Wolfgang Rösner

Johannes Kretz

Andrew Graham

Josef Willer

Volker Lehmann

Reinhard J Stengl

Manfred Engelhardt

Georg Braun

Hermann Wendt

Heinz Hoenigschmid

Hans Reisinger

Rainer Bruchhaus

Richard Johannes Luyken

Wolfram Wersing

Harald Bachhofer

Andreas Spitzer

Johannes Luyken

Dana Pitzer

Robert Primig

Ulrike Gruning

Holger Goebel

Marc Ullmann

Werner Simbürger

Hyang-Sook Klose, Legal Representative

The invention relates to a vertical integrated component, a component arrangement and a method for production of a vertical integrated component. The vertical integrated component has a first electrical conducting layer, a mid layer, partly embodied from dielectric material on the first electrical conducting layer, a second electrical conducting layer on the mid layer and a nanostructure integrated in a through hold introduced in the mid layer. A first end section of the nanostructure is coupled to the first electrical conducting layer and a second end section is coupled to the second electrical conducting layer. The mid layer includes a third electrical conducting layer between two adjacent dielectric partial layers, the thickness of which is less than the thickness of at least one of the dielectric partial layers.

Vertically integrated field-effect transistor having a nanostructure therein

The invention provides in a preferred embodiment an electronic component comprising a first conductive layer, a non-conductive layer and a second conductive layer. A hole is etched through the non-conductive layer. A nanotube, which is provided in said hole, links the first conductive layer to the second conductive layer in a conductive manner.

Electronic component comprising an electrically conductive connection consisting of carbon nanotubes and a method for producing the same

A multiplicity of nanotubes are applied to at least one external chip metal contact of an electronic chip in order to make contact between the electronic chip and a further electronic chip.

Electronic chip and electronic chip assembly

A nonvolatile memory cell, memory cell arrangement, and method for production of a nonvolatile memory cell is disclosed. The nonvolatile memory cell includes a vertical field-effect transistor (FET). The FET contains a nanoelement arranged as a channel region and an electrically insulating layer. The electrically insulating layer at least partially surrounds the nanoelement and acts as a charge storage layer and as a gate-insulating layer. The electrically insulating layer is arranged such that electrical charge carriers may be selectively introduced into or removed from the electrically insulating layer and the electrical conductivity characteristics of the nanoelement may be influenced by the electrical charge carriers introduced into the electrically insulating layer.

Non-volatile memory cell, memory cell arrangement and method for production of a non-volatile memory cell

The state is read out from the ferroelectric transistor or stored in the ferroelectric transistor. During the read-out or storage of the state, at least one further ferroelectric transistor in the memory matrix is driven in such a way that it is operated in its depletion region.

Method for reading out or in a status from or to a ferroelectrical transistor of a memory cell and memory matrix

The state of a ferroelectric transistor in a memory cell is read or stored, and the threshold voltage of further ferroelectric transistors in further memory cells in the memory matrix is increased during the reading or storing, or is increased permanently. A memory configuration including ferroelectric memory cells is also provided.

Memory configuration and method for reading a state from and storing a state in a ferroelectric transistor

A magnetic memory unit having a first magnetizable electrode, a second magnetizable electrode, and at least one nanotube arranged between the electrodes in a longitudinal direction and coupled to the first electrode by a first longitudinal end and to the second electrode by a second longitudinal end. A storage information item is stored in the memory unit in a nonvolatile fashion by setting a magnetization direction of one of the magnetizable electrodes by applying an external magnetic field.

Magnetic memory unit and magnetic memory array

Method for producing a silicon capacitor

A thin-film technology multi-layer capacitor with enhanced capacitance and/or reduced space requirement. The dielectric layers of which are alternately disposed between electrode layers on a substrate. Through alternate electrode layer connections, parallel interconnection of the individual capacitor layers is obtained. The result is that the individual capacitances are additive, while the temperature response can be optimized by a suitable choice or combination of different dielectric layers.

Multilayer capacitor with high specific capacitance and production

Growing community of inventors

Unterhaching, Germany

Wolfgang Hönlein