Infineon Technologies Ag

Green Mountain Semiconductor Inc.

Qimonda Ag

Other

Infineon Technologies North America Corp.

Qimonda North America Corporation

Wolfgang Hokenmaier

Ryan A Jurasek

Donald W Labrecque

Steffen Loeffler

Jacob Bucci

John Atkinson Fifield

Thomas Vogelsang

Christopher P Miller

Gerd Frankowsky

Gunther Lehmann

David R Hanson

Klaus Hummler

Ralf Klein

Michael A Killian

Jochen Hoffmann

Peter Thwaite

Margaret Freebern

Helmut Seitz

Khaled Fekih-Romdhane

Aaron D Willey

Harald Lorenz

Andre Sturm

Farrukh Aquil

Jochen Hoffman

A novel architecture provides many of the advantages of the array and datapath architecture of DRAM products that do not utilize ECC (error correction code) functionality, while simultaneously allowing the flexible deployment of ECC error correction as needed. Aspects of the disclosure enable the minimization of write and read latency typically introduced by the implementation of ECC error correction. Sharing of circuit components between neighboring memory regions is also introduced, which allows for a reduction in circuit area as well as a reduction in loading on speed-critical data bus wiring, which improves overall performance. A very fast single error correct (SEC) and double error detect (DED) read-out for real-time system-level awareness is also provided.

Flexible, low-latency error correction architecture for semiconductor memory products

Techniques are disclosed for artificial neural network functionality within dynamic random-access memory. A plurality of dynamic random-access cells is accessed within a memory block. Data within the plurality of dynamic random-access cells is sensed using a plurality of sense amplifiers associated with the plurality of dynamic random-access cells. A plurality of select lines coupled to the plurality of sense amplifiers is activated to facilitate the sensing of the data within the plurality of dynamic random-access cells, wherein the activating is a function of inputs to a layer within a neural network, and wherein a bit within the plurality of dynamic random-access cells is sensed by a first sense amplifier and a second sense amplifier within the plurality of sense amplifiers. Resulting data is provided based on the activating wherein the resulting data is a function of weights within the neural network.

Artificial neural network functionality using dynamic random-access memory

Artificial neural network functionality within dynamic random-access memory

A highly configurable, extremely dense, high speed and low power artificial neural network is presented. The architecture may utilize DRAM cells for their density and high endurance to store weight and bias values. A number of primary sense amplifiers along with column select lines (CSLs), local data lines (LDLs), and sense circuitry may comprise a single neuron. Since the data in the primary sense amplifiers can be updated with a new row activation, the same hardware can be reused for many different neurons. The result is a large amount of neurons that can be connected by the user. Training can be done in hardware by actively varying weights and monitoring cost. The network can be run and trained at high speed since processing and/or data transfer that needs to be performed can be minimized.

Dynamic random-access memory with embedded artificial neural network functionality

An extremely dense, high speed, and low power content addressable DRAM is presented. To enable a parallel searching, a data word to be searched may be driven onto column select lines (CSLs) of a DRAM array. Although two or more primary sense amplifiers typically are not connected at the same time to the same local data line during operation of a DRAM, in various embodiments presented herein, some or all sense amplifiers in a DRAM can be activated simultaneously to enable maximum parallelism with local data line sharing being explicitly allowed. Using this architecture, a data word can be simultaneously searched in all banks and with multiple wordlines. Since no input/output transactions are required and no data needs to be driven from the bank during execution of a search, overall current, and thus power usage, can be reduced.

Content addressable dynamic random-access memory with parallel search functionality

A memory including an array of memory cells and a control circuit. The control circuit is configured to control partial array self refreshes and to switch from one partial array self refresh to another partial array self refresh. Data in memory cells that are refreshed via the one partial array self refresh and refreshed via the other partial array self refresh is retained in the memory cells from before a first switch from the one partial array self refresh to the other partial array self refresh to after the first switch.

Memory that retains data when switching partial array self refresh settings

An integrated circuit includes a memory array, first pads, and second pads. The integrated circuit is configured to operate in a first mode and in a second mode. The first mode includes receiving data signals on the first pads and address signals on the second pads to access the memory array. The second mode includes receiving multiplexed data signals and address signals on the first pads to access the memory array.

Integrated circuit including selectable address and data multiplexing mode

A memory including periphery circuitry configured to support multiple banks of memory cells. The periphery circuitry includes switches that are set to put the periphery circuitry into a first mode to support a portion of the multiple banks of memory cells and a second mode to support all of the multiple banks of memory cells.

Memory including periphery circuitry to support a portion or all of the multiple banks of memory cells

A temperature control circuit, comprising: a plurality of temperature sensors each configured to measure a temperature of a corresponding memory chip chosen from a plurality of memory chips, and to generate a sensor output signal that is set to a first voltage if the measured temperature of the corresponding memory chip meets a temperature requirement, and is set to a floating voltage if the measured temperature of the corresponding memory chip does not meet the temperature requirement, the sensor output signal being connected to an intermediate node; a current source connected to the intermediate node; and a control circuit configured to provide chip control signals to the plurality of memory chips.

System and method for monitoring temperature in a multiple die package

A method for reducing defect leakage current in a semiconductor memory device comprising a plurality of memory banks, each memory bank comprising a plurality of memory arrays and sense amplifier columns comprising a plurality of sense amplifiers, wherein there is a sense amplifier column positioned between and shared by memory arrays on opposites thereof. At least one bank-specific isolation control signal is independently generated for each of the plurality of memory banks depending on existence and location of an anomalous bitline leakage in a memory bank. The at least one bank-specific isolation control signal is supplied to at least one sense amplifier column in the corresponding memory bank to isolate at least one side to at least one memory array that is in an unselected state in a corresponding memory bank.

Reducing leakage current in memory device using bitline isolation

An apparatus for controlling generation of pulses for refresh operations of a memory device having a pad to transfer information and to receive signals from an external interface. The apparatus includes a switch, coupled to a current source and to the pad receiving signals from the external interface. The switch outputs one of the signals from the current source or the pad in response to a switch control signal. An oscillator is coupled to the switch and generates the refresh operation pulses in response to the output from the switch.

Method and apparatus for an oscillator within a memory device

A self-refresh module includes an oscillator configured to provide a first signal having a first frequency, a trimming divider configured to trim the first signal to provide a second signal having a second frequency, and a temperature sensor configured to sense a temperature of the memory device and provide a temperature signal. The self-refresh module includes a temperature look-up table configured to receive the temperature signal and provide a third signal based on the temperature signal, and a temperature divider configured to provide a self-refresh pulse signal based on the second signal and the third signal.

Temperature dependent self-refresh module for a memory device

A memory circuit comprises a memory and a first test circuit coupled to the memory. The first test circuit is configured to compare data read from memory cells with expected data for the memory cells to provide a first set of pass/fail signals for the memory cells, compress the first set of pass/fail signals for the memory cells into a second pass/fail signal, latch the second pass/fail signal in response to a data valid signal, maintain the latch of the second pass/fail signal if the second pass/fail signal indicates a failed test, combine the second pass/fail signal and a third pass/fail signal of a second test circuit to provide a fourth pass/fail signal, and pass the fourth pass/fail signal to a third test circuit.

Memory having test circuit

A memory circuit comprises a memory including a memory array, a twin cell mode predecoder, and a row address predecoder. The memory array comprises word lines. The twin cell mode predecoder is configured for selecting one of four word line activation configurations for the memory array. The four word line activation configurations include three twin cell word line activation configurations and a single cell word line activation configuration. The row address predecoder is configured for selecting one of four word lines if the single cell word line activation configuration is selected.

Memory with selectable single cell or twin cell configuration

Techniques and apparatus that may be utilized to reduce current consumption during refresh cycles of DRAM devices that utilize wordline segments are provided. Rather than activate and subsequently de-activate (pre-charge) a master wordline each time a corresponding wordline segment is refreshed, the master wordline may remain activated while corresponding wordline segments are refreshed.

Growing community of inventors

Burlington, VT, United States of America

Wolfgang Hokenmaier