Siemens Aktiengesellschaft

Infineon Technologies Ag

Soitec

Wolfgang Hoenlein

Volker Lehmann

Reinhard J Stengl

Josef Willer

Roland Thewes

Hermann Wendt

Gerhard Enders

Dietrich Widmann

Franz Hofmann

Richard Ferrant

Walter Hartner

Martin Franosch

Carlos Mazure

Hans Reisinger

Siegfried Schwarzl

Joerg Vollrath

Helmut Klose

Thomas Peter Haneder

Hanno Melzner

Herbert Schaefer

Guenther Schindler

Gerrit Lange

Harald Bachhofer

Hans-Willi Meul

Andreas Spitzer

Hofmann Franz

Michael Boy

The invention relates to a sense amplifier for sensing and amplifying data stored in a memory cell, the sense amplifier being connected between a bit line (BL) and a reference bit line complementary (/BL) to the first bit line and comprising: a sense circuit (SC) capable of providing an output indicative of the data stored in the memory cell; and a precharge and decode circuit (PDC) comprising a pair of dual gate transistors (T, T) for precharging the first and second bit lines during a precharge operation and for transferring the output provided by the sense circuit to a data line (LIO,/LIO) during a read operation.

Sense amplifier with dual gate precharge and decode transistors

The present invention relates to a method for the manufacture of a semiconductor device by providing a first substrate; providing a doped layer in a surface region of the first substrate; providing a buried oxide layer on the doped layer; providing a semiconductor layer on the buried oxide layer to obtain a semiconductor-on-insulator (SeOI) wafer; removing the buried oxide layer and the semiconductor layer from a first region of the SeOI wafer while maintaining the buried oxide layer and the semiconductor layer in a second region of the SeOI water; providing an upper transistor in the second region by forming a back gate in or by the doped layer; and providing a lower transistor in the first region by forming source and drain regions in or by the doped layer.

Fully depleted SOI device with buried doped layer

A resistor cascade has a multiplicity of electrical resistors connected in series, and each electrical resistor has at least one single-walled carbon nanotube.

Resistor cascade for forming electrical reference quantities and analog/digital converter

The crystallization temperature of a ferroelectric layer ( ) (dielectric) for a storage capacitor can be lowered by applying a very thin (CeO layer ( ) to a first platinum electrode layer ( ) of the storage capacitor before the ferroelectric layer is deposited. The dielectric layer ( ) deposited in amorphous state is then crystallized by a temperature treatment step at a temperature in the range between 590&deg; C. and 620&deg; C. A second electrode layer ( ) is then applied to complete the storage capacitor.

Method of manufacture of a capacitor with a dielectric on the basis of strontium-bismuth-tantalum

For manufacturing a capacitor, in particular for a dynamic memory cell arrangement, a trench is etched in a substrate. In the trench, a layer sequence is produced that contains, in alternating fashion, layers of doped silicon and germanium-containing layers. By anisotropic etching, the surface of the semiconductor substrate (12) is exposed in the region of the trench floor. The trenches are filled with a conductive support structure (20). The germanium-containing layers are removed selectively to the layers of doped silicon. The exposed surface of the layers of doped silicon (17) and of the support structure (20) are provided with a capacitor dielectric (22), onto which is applied a counter-electrode (23).

Method for manufacturing a capacitor for a semiconductor arrangement

A capacitor in a semiconductor configuration, especially a DRAM, includes an electrode structure having a plurality of spaced-apart elements being electrically connected with a connecting structure and all including p-conductive material with a doping &gt;10.sup.10 cm.sup.-3. The elements of the electrode structure are either stacked or disposed side by side and may be cup-shaped. In a production process, a layer sequence of alternatingly one p.sup.- -doped and one p.sup.+ -doped layer is produced, which receives an opening through the use of anisotropic etching. At least in a peripheral region of the opening, a p.sup.+ -zone is created, which connects the layer sequence and forms the connecting structure. Next, the p.sup.- -doped layers are etched selectively to the p.sup.+ -doped layers, a capacitor dielectric is deposited, and a counterelectrode is produced.

Capacitor in a semiconductor configuration and process for its production

A circuit structure having at least one capacitor and a method for the manufacture thereof. The capacitor is constructed of a doped, single-crystal silicon substrate (1) that is provided with a plurality of hole openings (3) by electrochemical etching in a fluoride-containing, acidic electrolyte wherein the substrate is connected as an anode. The capacitor is further constructed of a dielectric layer (4) and of a conductive layer (5) as a cooperating electrode.

Circuit structure having at least one capacitor and a method for the

A method used in manufacturing a cubically integrated circuit arrangement. A silicon wafer, wherein through pores are produced by electrochemical etching are insulated from the silicon wafer, and are provided with conductive fills, is secured as a carrier plate (24) to a substrate (21) that has components and that is integrated in a cubically integrated circuit arrangement. Terminal pads (25) that are electrically connected to conductive fills and that are arranged on the surface of the carrier plate (24) thereby meet contacts (23) to the components that are arranged at the surface of the substrate (21) adjoining the carrier plate (24) and that are firmly connected thereto.

Method for manufacturing a cubically integrated circuit arrangement

Through-holes are formed in a substrate wafer by electrochemical etching, so that a perforated, self-supporting layer of n-doped, monocrystalline silicon arises. An n-doped region and a p-doped region that form a pn-junction and that both adjoin a first principal face of the self-supporting layer are produced in the self-supporting layer. A contact to the n-doped region and a contact to the p-doped region are formed on the first principal face, so that the pn-junction can be interconnected as solar cell into which the light incidence can occur via a second principal face lying opposite the first.

Method for manufacturing a solar cell from a substrate wafer

Rod-shaped or cylindrical structures in the nm range on a substrate of silicon are manufactured. A first cylinder of silicon is selectively epitaxially deposited in the hole of a mask layer of oxide, and the mask layer is removed. The silicon is then oxidized to form an oxide layer having such a thickness that a thinner, second cylinder of silicon having practically the same height as the first cylinder remains. In a last step, this oxide layer is removed, so that the second cylinder forms a freestanding silicon rod on the surface of the substrate.

Method for manufacturing rod-shaped silicon structures

A multi-chip module has a carrier (21) of monocrystalline silicon whose surface is at least partially enlarged by anodic electro-chemical etching in a fluoride-containing acidic electrolyte. At least one capacitor (23) that has a dielectric layer and a conductive layer is arranged on the enlarged surface of the carrier (21), whereby the carrier (21) and the conductive layer act as capacitor electrodes.

Multi-chip module

For manufacturing a component with porous silicon, two highly doped regions with a lightly doped region arranged between them are formed in a silicon wafer. The dopant concentrations are thereby set such that porous silicon arises in the lightly doped region in a subsequent anodic etching. Light-emitting diodes or light-controlled bipolar transistors can be manufactured in this way.

Method for manufacturing a component with porous silicon

A self-supporting layer of n-doped monocrystalline silicon is stripped from a substrate wafer of n-doped, monocrystalline silicon by electrochemical etching for manufacturing a solar cell. Holes are formed in the substrate wafer by electrochemical etching, particularly in a fluoride-containing, acidic electrolyte wherein the substrate wafer is connected as an anode. When a depth of the holes that essentially corresponds to the thickness of the self-supporting layer is reached, the process parameters of the etching are modified such that the self-supporting layer is stripped as a consequence of the holes growing together. The solar cell is manufactured from the self-supporting layer, and the method can be applied repeatedly on the same substrate wafer for stripping a plurality of self-supporting layers.

For manufacturing an electrically conductive tip composed of a doped semiconductor material, a mask layer is produced on a substrate composed of the semiconductor material. This mask layer contains a material at least at its surface and directly on the substrate whereon the semiconductor material does not grow in a selective epitaxy. An opening wherein the surface of the substrate lies exposed is produced in the mask layer. The electrically conductive tip is produced by a selective epitaxy on the exposed surface of the substrate such that the layer growth in the direction parallel to the surface of the substrate is lower than in the direction perpendicular to the surface of the substrate.

Growing community of inventors

Unterhaching, Germany

Wolfgang Hoenlein