Infineon Technologies Ag

Qimonda Ag

Siemens Aktiengesellschaft

Infineon Technologies LLC

United Test and Assembly Center Limited

Utac - United Test and Assembly Test Center Ltd.

Wolfgang Hetzel

Jochen Thomas

Ingo Wennemuth

Werner Josef Reiss

Thorsten Scharf

Swee Kah Lee

Kian Teng Eng

Stefan Macheiner

Peter Weitz

Chan Lam Cha

Pang Hup Ong

Anton Legen

Norbert Martin Haueis

Rodel Manalac

Soo Pin Chow

Fung Leng Chen

Seong Kwang Brandon Kim

Stefan Schmausser

Peter Eigenstetter

Alfred Schallert

Georg Schlaffer

Friedrich Wanninger

Yi-Sheng Anthony Sun

Wee Lim Cha

Florian Ammer

Bryan Soon Hua Tan

Denver Paul C Castillo

A semiconductor package includes: a lead frame having a plurality of blocks of uniform size and laterally spaced apart from one another with uniform spacing; a first semiconductor die attached to a first group of the blocks; electrical conductors connecting a plurality of input/output (I/O) terminals of the first semiconductor die to a second group of the blocks, at least some blocks of the second group being laterally spaced outward from the blocks of the first group; and a mold compound encapsulating the first semiconductor die and the electrical conductors. Corresponding methods of producing the semiconductor package are also described.

Lead frame-based semiconductor package

A semiconductor component () has an interposer substrate () as stack element of a semiconductor component stack (). The interposer substrate () has, on one of the interposer substrate sides (), a semiconductor chip protected by plastics composition () in its side edges (). An interposer structure () partly covered by a plastics composition () is arranged on the interposer side () opposite to the semiconductor chip (). Edge regions () of the interposer substrate () remain free of any plastics composition () and have, on both interposer sides () external contact pads () which are electrically connected to one another via through contacts ().

Semiconductor component comprising an interposer substrate

A method of mounting a semiconductor die on a substrate with a solder mask on a first surface includes placing a die on the solder mask, and mounting the die to the substrate by applying pressure and heat. The applied pressure ranges from a bond force of approximately 5 to 10 kgf, the heat has a temperature range from approximately 150 to 200&#xb0; C. and the pressure is applied for a range of approximately 1 to 10 seconds.

Semiconductor package and method of attaching semiconductor dies to substrates

A semiconductor device with a plastic package molding compound, a semiconductor chip and a leadframe is disclosed. In one embodiment, the semiconductor chip is embedded in a plastic package molding compound. The upper side of the semiconductor chip and the plastic package molding compound are arranged on a leadframe. Arranged between the leadframe and the plastic package molding compound with the semiconductor chip is an elastic adhesive layer for the mechanical decoupling of an upper region from a lower region of the semiconductor device.

Semiconductor device with plastic package molding compound, semiconductor chip and leadframe and method for producing the same

A BGA package is disclosed including a base IC structure having a base substrate, with an opening running length-wise there through. A first semiconductor chip is mounted face-down on the base substrate so the bond pads thereof are accessible through the opening. The package also includes a secondary IC structure including a secondary substrate, having an opening running there through, and a second semiconductor chip. The second chip is mounted face-down on the secondary substrate so that the bond pads thereof are accessible through the opening in the secondary substrate. An encapsulant fills the opening in the secondary substrate and forms a substantially planar surface over the underside of the secondary substrate. The substantially planar surface is mounted to the first chip of the base IC structure through an adhesive. Wires connect a conductive portion of the secondary IC structure to a conductive portion of the base IC structure.

Multi-chip ball grid array package and method of manufacture

The present invention relates to a multi-chip device comprising a substrate having a first surface on which a number of first contact elements is provided, a plurality of integrated circuit chips arranged in a chip stack which is arranged on a second surface of the substrate opposing the first surface, wherein each of the chips having a surface on which a number of second contact elements are provided, wherein a first one of the chips and the second contact elements thereon is arranged such that its second contact elements are uncovered by any of the chips or by the substrate and face towards the second surface of the substrate; and connecting elements which are arranged such as to connect at least one of the first contact elements of the substrate and at least one of the second contact elements of the first chip.

Multi-chip device and method for producing a multi-chip device

A stackable packaged chip includes a substrate with a conductive wiring formed therein or thereon. The substrate further includes a plurality of substrate contact pads arranged around a periphery portion of the substrate. A chip mounted on the substrate including contact pads that are electrically connected with the conductive wiring of the substrate, and a ring surrounding edges of the chip are also included. The ring is formed from an electrically insulating material and includes a plurality of openings, each opening adjacent a substrate contact pad to allow for electrical connection to the chip though the substrate contact pad.

Stackable single package and stacked multi-chip assembly

A method of stacking semiconductor chips includes providing four semiconductor chips that each include a top surface with central bond pads. Each of the bond pads is electrically coupled to second bond pads located in a peripheral portion of the semiconductor chip through a conductive layer. The first and the second semiconductor chips are arranged alongside one another on a carrier substrate. The second bond pads from the first and second semiconductor chips are bonded to corresponding landing pads on the substrate. The third semiconductor chip is then stacked over the first semiconductor chip and the fourth semiconductor chip over the second semiconductor chip. The second bond pads of the third and fourth semiconductor chips can then be bonded to contact pads of the substrate. The substrate can then be separated into a first stack that includes the first and third semiconductor chips and a second stack that includes the second and fourth semiconductor chips.

Method for manufacturing a stack arrangement of a memory module

An electronic component has a chip stack with a first semiconductor chip, a second semiconductor chip, and a large number of flat conductors configured in between the first semiconductor chip and the a second semiconductor chip. The flat conductors have a central section on which the semiconductor chips are mounted. First bonding connections connect the first semiconductor chip to inner sections of the flat conductors. Second bonding connections connect the second semiconductor chip to transitional sections of the flat conductors. The outer sections of the flat conductors project out of a package.

Electronic component having stacked semiconductor chips in parallel, and a method for producing the component

A stack arrangement of discrete components includes a carrier substrate and at least two discrete components, e.g., memory chips. The carrier substrate has line conductor structures and contact pads. Each of the discrete components includes centrally disposed bond pads and a metallic coating, which is electrically connected to the centrally disposed bond pads. The metallic coating is disposed on an active surface area of each discrete component. A protective structure overlies a central region of the discrete component. In the preferred embodiment, the metallic coatings of each discrete component are identical. Preferably, the discrete components are stacked on the carrier substrate so as to have the same orientation, so that the protective structure serves as a spacer between the discrete components. Further, the metallic coating is electrically coupled to the carrier substrate.

Stack arrangement of a memory module

The invention relates to an electronic device having a stack of semiconductor chips, and to a method for the production thereof. A first semiconductor chip is arranged on a rewiring substrate, and at least one semiconductor stack chip is arranged on the first semiconductor chip. A rewiring plane is arranged between the semiconductor chips. The contact areas of the semiconductor chips are connected to external contacts of the device by the rewiring plane and the rewiring substrate.

Electronic device having a stack of semiconductor chips and method for the production thereof

The fully automatic conveying system, a so-called handler, picks up, tests, inscribes, and packages finished mounted components in a semiconductor manufacturing plant. Each component is assigned a dedicated data record and it is accordingly automatically deposited in a selected package. The component is thus inscribed, classified, and packaged with a specific class identifier in dependence on the preceding tests.

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Nattheim, Germany

Wolfgang Hetzel