Texas Instruments Corporation

Texas Instruments Incorporated Deutschland, Gmbh

Wolfgang Heinz Schwartz

Joel Martin Halbert

Doug Weiser

Christoph Andreas Othmar Dirnecker

Karsten Jens Spinger

Joseph Anthony DeSantis

Philipp Steinmann

Vladimir Frank Drobny

Alfred Haeusler

Manfred Schiekofer

Berthold Georg Staufer

Thomas Scharnagl

Bernhard Benna

Karl-Heinz Kraus

Michael Kraus

Dirk Robert Walter Leipold

In one example an electronic device includes a first resistor and a second resistor. The first resistor includes a first resistive layer located over a substrate, the first resistive layer having a first sheet resistance. The second resistor includes a first portion of a second resistive layer located over the substrate, the second resistive layer having a second sheet resistance different from the first sheet resistance. The first resistive layer is located between the substrate and a second noncontiguous portion of the second resistive layer.

Method and structure for dual sheet resistance trimmable thin film resistors

A method of forming an electronic device includes forming an opening through a dielectric layer located over a first resistive layer, the first resistive layer having a first sheet resistance. A second resistive layer is deposited over the dielectric layer and into the opening. The second resistive layer has a second sheet resistance different from the first sheet resistance. A portion of the second resistive layer is removed, thereby forming first and second noncontiguous portions of the second resistive layer, wherein the second portion of the second resistive layer contacts the first resistive layer.

A method for making a super &#x3b2; NPN (SBNPN) transistor includes depositing a tetraethyl orthosilicate (TEOS) layer on a P type epitaxial layer; depositing a nitride layer on the TEOS layer; patterning an emitter region of the SBNPN transistor by selectively etching away portions of the nitride layer and the TEOS layer; depositing a second TEOS layer on top of the nitride layer, along sides of the nitride layer and the TEOS layer, and on top of the P type epitaxial layer; and implanting the P type epitaxial layer through the second TEOS layer with N type ions to form the emitter region of the SBNPN transistor.

High performance super-beta NPN (SBNPN)

An integrated circuit includes a higher sheet resistance resistor and a lower sheet resistance resistor, disposed in a same level of dielectric layers of the integrated circuit. The higher sheet resistor has a body region and head regions in a higher sheet resistance layer. The lower sheet resistor has a body region and head regions in a lower sheet resistance layer, which is thicker than the higher sheet layer. The higher sheet resistor has an upper head layer contacting the higher sheet layer at each head region of the higher sheet layer. Each upper head layer has a same composition and thickness as the lower sheet layer of the lower sheet resistor. The lower sheet resistor is free of head layers over the lower sheet resistance layer.

Method and structure for dual sheet resistance trimmable thin film resistors at same level

Method of forming an electrical contact between a support wafer and a surface of a top silicon layer of a silicon-on-insulator wafer. The method comprises etching a cavity into the top silicon layer and the insulator layer. A selective epitaxial step is performed for growing an epitaxial layer of silicon inside the cavity up to the surface of the top silicon layer. An electrical device comprising an electrical contact between a support wafer and a surface of a top silicon layer of a silicon-on-insulator wafer formed according to the inventive method.

Method of forming an electrical contact between a support wafer and the surface of a top silicon layer of a silicon-on-insulator wafer and an electrical device including such an electrical contact

A method of manufacturing a semiconductor device, the method comprising: taking an SOI substrate comprising a bulk substrate, a buried insulating layer and an active layer, and implanting the bulk substrate from the side of and through the insulating layer and the active layer so as to generate an area having an increased doping concentration in the bulk substrate at the interface between the bulk substrate and the insulating layer.

Tuning of SOI substrate doping

The invention relates to an integrated CMOS circuit for use at high frequencies with active CMOS components ( ) and passive components ( ). The active CMOS components ( ) are formed in a semiconductor substrate ( ) which has a specific resistivity in the order of magnitude of k&OHgr;cm. In the semiconductor substrate ( ), and under the active CMOS components ( ), a buried layer ( ) is formed which has a specific resistivity in the order of magnitude of &OHgr;cm. The passive components ( ) are formed in or on a layer ( ) of insulating material which is arranged on the semiconductor substrate ( ). A conducting contact layer ( ) is arranged on that surface of the semiconductor substrate ( ) which is not facing the layer ( ) of insulating material.

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Ergolding, Germany

Wolfgang Heinz Schwartz