Infineon Technologies Ag

Siemens Aktiengesellschaft

Wolfgang H&ouml;nlein

Hans Reisinger

Reinhard J Stengl

Thomas Peter Haneder

Volker Lehmann

Hermann Wendt

Harald Bachhofer

Manfred Engelhardt

Walter Hartner

Franz Kreupl

Martin Franosch

Rainer Bruchhaus

Frank S Hintermaier

Helmut Klose

Till Schl&ouml;sser

Richard Johannes Luyken

G&uuml;nther Schindler

Carlos Mazure-Espejo

Gerrit Lange

Herbert Sch&auml;fer

A field-effect transistor that having a nanowire, which forms a source region, a channel region and a drain region of the field-effect transistor, the nanowire being a semiconducting and/or metallically conductive nanowire. The field-effect transistor also has at least one nanotube, which forms a gate region of the field-effect transistor, the nanotube being a semiconducting and/or metallically conductive nanotube. The nanowire and the nanotube are arranged at a distance from one another or set up in such a manner that it is substantially impossible for there to be a tunneling current between the nanowire and the nanotube, and that the conductivity of the channel region of the nanowire can be controlled by means of a field effect as a result of an electric voltage being applied to the nanotube.

Field effect transistor

A ferroelectric transistor suitable as a memory element has a first gate intermediate layer and a first gate electrode disposed on the surface of a semiconductor substrate and disposed between source/drain regions. The first gate intermediate layer contains at least one ferroelectric layer. In addition to the first gate intermediate layer, a second gate intermediate layer and a second gate electrode are configured between the source/drain regions. The second gate intermediate layer contains a dielectric layer. The first gate electrode and the second gate electrode are connected to each other via a diode structure.

Ferroelectric transistor, use thereof in a memory cell configuration and method of producing the ferroelectric transistor

A capacitor for a semiconductor configuration and a method for producing a dielectric layer for the capacitor. The dielectric layer consists of cerium oxide, zirconium oxide, hafnium oxide or various films of the materials.

Capacitor for semiconductor configuration and method for fabricating a dielectric layer therefor

An integrated circuit configuration, in particular is a DRAM cell configuration, includes a capacitor disposed on a first substrate and a portion with a contact disposed on a second substrate. The first substrate is connected to the second substrate, with the contact adjoining the capacitor. The first substrate and the second substrate can be connected essentially in an unadjusted manner, if capacitor elements are distributed over the first substrate and a contact surface of the contact is so large that when the substrates are connected, the contact in each case adjoins at least one of the capacitor elements, which then defines the capacitor. The capacitor may include a plurality of capacitor elements, which makes its capacitance especially high. A method is also provided for producing the integrated circuit configuration.

Integrated circuit configuration having at least one capacitor and method for producing the same

The integrated semiconductor memory configuration has a semiconductor body in which selection transistors and storage capacitors are integrated. The storage capacitors have a dielectric layer configured between two electrodes. At least the upper electrode is constructed in a layered manner with a platinum layer, that is seated on the dielectric layer, and a thicker, base metal layer lying above the platinum layer.

Easy to manufacture integrated semiconductor memory configuration with platinum electrodes

A manufacturing method for a capacitor in an integrated memory circuit includes initially depositing a first conducting layer and an auxiliary layer acting as an etch-stop onto a carrier. Then a layer sequence which contains alternating layers of the first material and a second material is produced on top of the first conducting layer and the auxiliary layer. The layer sequence may, in particular, have p,/p,silicon layers or silicon/germanium layers. A layer structure with a base of a capacitor to be produced is formed from the layer sequence. Sides of the layer structure are provided with a conducting supporting structure. An opening is formed inside the layer structure, all the way down to the auxiliary layer and then the auxiliary layer and the layers made of the second material are removed. A free surface of the layers made of the first material and the supporting structure are provided with a capacitor dielectric onto which a counter electrode is applied.

Manufacturing method for a capacitor in an integrated memory circuit

Growing community of inventors

Unterhaching, Germany

Wolfgang Hönlein

Growing community of inventors

Unterhaching, Germany

Wolfgang H&ouml;nlein

Wolfgang Hönlein