Rca Inc.

Harris Corporation

Wolfgang F Dietz

John M Neilson

Robert Joseph Gries

Leroy W Nero

John Charles Peer

Sammy S Henig

The performance of COMFET-based electrical switches may be improved by connecting a MOSFET substantially in parallel with the COMFET. In a monolithic embodiment, a MOSFET drain region may be added to a surface of a COMFET and shorted to the emitter region of the COMFET. The invention decreases the turn-off time of the COMFET, reduces the discontinuity at current direction reversal and increases the latch-up current of a semiconductor switch.

COMFET switch and method

In a video display apparatus, the high voltage generating circuitry responds to trigger pulses derived from horizontal deflection retrace-related pulses. During normal horizontal deflection operation, the trigger pulses produced are of sufficient amplitude to cause normal triggering of the high voltage generating circuits resulting in normal high voltage levels being produced. Under abnormal horizontal deflection operation in which the horizontal deflection current is not produced, the trigger pulses will be of insufficient amplitude to trigger the high voltage generating circuit, and hence no high voltage level is produced.

Video apparatus deflection loss protection

A deflection circuit generates a deflection current at a scan frequency selected from any one of at least two ranges of frequencies. When the scan frequency is selected from the first range, only a first S-capacitor provides S-correction. When the scan frequency is selected from a lower second range, a series connected FET switch couples a second S-capacitor across the first S-capacitor. A DC average voltage is developed at a junction between the first and second S-capacitors. A resistor coupled to the second S-capacitor causes the second S-capacitor to be charged to the average DC voltage to prevent the average DC voltage from developing across the main current conducting electrodes of the FET switch when the FET switch is nonconductive. The FET switch is controlled by an output voltage of a comparator. The comparator is responsive to a signal that is indicative of the frequency range from which the scan frequency is selected. The comparator utilizes positive feedback to provide hysteresis that prevents switch bounce of the FET switch when the signal is in the vicinity of the threshold of the comparator.

S-capacitance switching circuit for a video display

A vertical rate parabolic voltage at a peak-to-peak amplitude that is adjustable is generated in an integrator from a sawtooth input voltage. The parabolic voltage at an output terminal of the integrator is applied to a source of a B+ operating voltage to form a parabolic component voltage of the B+ operating voltage that controls the amplitude of a trace current in a horizontal deflection circuit output stage. The parabolic voltage is adjusted in peak-to-peak amplitude to provide east-west pincushion correction of the raster. The minimum level of the parabolic voltage in each vertical period is automatically maintained at an unchanged level that is approximately zero volts throughout the range of east-west adjustment. Because the minimum level of the parabolic voltage remains unchanged, the maximum level of the B+ operating voltage, a level that occurs in the center of each vertical interval, also remains unchanged throughout the range of east-west adjustment. In this way, the width of the raster is unaffected by adjustment of the peak-to-peak amplitude of the parabolic component voltage of the B+ operating voltage.

Parabolic voltage generating circuit

A television centering circuit includes a non-linear conduction network coupled in series with an inductance. The series arrangement is conductively coupled in parallel with a horizontal deflection winding. A control circuit for the non-linear conduction network utilizes negative feedback to sense and control the current in the inductance when the current is of a first polarity, thereby regulating the average value of the current in the inductance and in the deflection winding to provide raster centering.

Raster positioning circuit for a deflection system

A phase-lock loop circuit of a television apparatus is synchronized by a horizontal synchronizing input signal. The phase-lock loop circuit includes a frequency-to-voltage converter that is responsive, during vertical trace, to the synchronizing input signal for generating a control voltage indicative of the frequency of the synchronizing input signal. During vertical trace, the control voltage varies the free running frequency of a controlled oscillator of the phase-lock loop circuit such that the free running frequency of the oscillator is directly related to the frequency of the input signal. During vertical retrace, the frequency-to-voltage converter is responsive to the oscillator output signal for generating the control signal that maintains the free running frequency of the oscillator substantially unchanged during vertical retrace. The phase of the output signal of the oscillator is controlled by a signal that is indicative of the phase difference between the oscillator output signal and the synchronizing input signal.

Synchronization circuit responsive to time-multiplexed signals

A video monitor includes apparatus for generating a horizontal blanking pulse accurately timed with respect to a horizontal image retrace interval. The leading edge of the blanking pulse is derived from a differentiated horizontal oscillator signal which is applied to one input of a gate having a threshold operating level. The lagging edge of the blanking pulse is generated when the amplitude of a horizontal flyback pulse applied to another input of the gate falls below the gate threshold level.

Video image blanking signal generator

An automatic S-correction circuit for a deflection circuit includes an active source of generally sawtooth current having an amplitude that is proportional to the deflection frequency. The sawtooth current and a deflection current that flows in a deflection winding are combined as a current flowing in an S-capacitor that develops a parabolic voltage. The amplitude of the parabolic voltage is automatically adjusted to be at a level that is required for maintaining proper S-correction for any deflection frequency within a continuous, wide range of frequencies.

S-correction circuit for a video display

A phase-lock loop circuit of a video display apparatus is synchronized by a horizontal synchronizing input signal. The phase-lock loop circuit includes a frequency-to-voltage converter that is responsive to the synchronizing input signal for generating a control voltage indicative of the frequency of the synchronizing input signal. A voltage-to-current converter responsive to the control voltage generates a control current that is indicative of the frequency of the input signal. The control current varies the free running frequency of a controlled oscillator of the phase-lock loop circuit such that the free running frequency of the oscillator is directly related to the frequency of the input signal. The phase of the output signal of the oscillator is controlled by a second control current that is indicative of the phase difference between the oscillator output signal and the synchronizing input signal. When the frequency of the input signal is lower than a predetermined frequency, the first control current is at a level that causes the free running frequency to be above a predetermined minimum frequency.

Circuit synchronized by a signal at a deflection frequency

An apparatus for generating a periodic resonant pulse voltage across an inductance includes first and second switches coupled together in a series cascode arrangement. The cascode arrangement applies a first voltage to an inductance for storing energy therein. A periodic switching signal is coupled to the second switch. Each cycle of the switching signal includes a turn-on portion and a turn-off portion. The initiation of the turn-off portion makes the second switch nonconductive to enable the inductance and a resonating capacitance to form a resonant circuit that generates a resonant pulse voltage at a terminal of the resonant circuit. A damper switch is coupled to the inductance for terminating the generation of the resonant pulse voltage at the end of the first interval, prior to the initiation of the turn-on portion of the switching signal. The voltage at the resonant circuit terminal is coupled to the control electrode of the first switch for supplying current thereto during conduction of the damper switch. This enables the first switch to conduct current from the inductance during conduction of the second switch.

Resonant switching apparatus using a cascode arrangement

A line deflection voltage regulator develops a regulated scan supply voltage. A line deflection circuit is coupled to the voltage regulator for generating line scanning current in a line deflection winding. The amplitude of the scanning current is dependent on the magnitude of the regulated scan supply voltage. A high voltage regulator develops a second regulated voltage. A high voltage generator is coupled to the high voltage regulator for generating an ultor output voltage at an ultor terminal. The magnitude of the ultor output voltage is dependent on the second regulated voltage. A high voltage control circuit is coupled in a feedback path between the high voltage generator and the high voltage regulator for developing a first ultor control voltage that is representative of the ultor output voltage to regulate the ultor output voltage. A second ultor control voltage that is representative of fluctuations in the ultor output voltage is developed at a point within the feedback path. The second control voltage is coupled to the line deflection voltage regulator for varying the regulated scan supply voltage to provide raster width regulation.

Raster width regulation circuit

An integrated circuit interface means for use in a television receiver comprises means including an interface terminal which gives an indication of whether the receiver is operating in a standard or nonstandard mode. Standard operating mode occurs during the reception of standard broadcast signals. Non-standard non-broadcast signals cause the receiver to operate in a non-standard mode. The interface means also comprises means coupled to the same interface terminal for providing a signal to the integrated circuit which manually selects the operating mode, thereby allowing the interface terminal to serve the dual function of indicating and selecting the receiver operating mode.

Integrated circuit interface in a vertical sync circuit

A transistor horizontal deflection circuit is energized from a source of unregulated direct voltage derived from the power mains but is conductively isolated therefrom. A switching voltage regulator couples the direct voltage source to the horizontal deflection circuit. The regulator includes a controllable switch serially coupled with the primary winding of a transformer and the source. The switch is controlled to maintain a constant voltage or energy level in the horizontal deflection circuit. A secondary winding conductively isolated from the primary is coupled across the deflection winding for forming a path for bidirectional current flow. The horizontal output transistor is coupled in parallel with the deflection winding for producing retrace pulses which are coupled to the primary winding for reducing the current in the controllable switch to zero during the retrace interval.

Commutated switched regulator with line isolation for transistor

A horizontal deflection circuit of a television receiver includes a horizontal deflection winding, a retrace capacitor and a trace switch comprising a damper diode and a horizontal output transistor. A horizontal oscillator provides a synchronized deflection rate square-wave voltage to a base-drive generator circuit for the horizontal output transistor. The base-drive generator circuit develops a forward biasing portion of the horizontal output transistor base-drive signal to maintain the transistor in saturated conduction during the latter portion of trace. The generator also develops a reverse biasing portion to initiate horizontal retrace after the output transistor collector current is cut off. A lapse of a turn-off delay time occurs from the initiation of the reverse biasing portion of the base-drive signal to the collector current cutoff instant. Energy is transferred from an unregulated input supply to television receiver load circuits through an inductance such as a flyback transformer. A controllable switch is coupled to the inductance. The switch is turned on within each deflection cycle to enable energy from the unregulated input supply to be stored in the inductance during the latter portion of the trace interval. A retrace pulse voltage applied to the inductance initiates the energy transfer interval. To regulate the energy transfer, the turn-off delay time of the horizontal output transistor is controlled, thereby controlling the initiation of the retrace and energy transfer interval.

Horizontal deflection circuit and power supply with regulation by

An SCR is one controllable switch thyristor in an SSVD circuit and the other is a triac. One electrode of each thyristor is grounded, and the gates of the thyristors are driven from the SSVD control circuit by pulse voltages relative to ground.

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New Hope, PA, United States of America

Wolfgang F Dietz