Ant Nachrichtentechnik Gmbh

Wolfgang Ehrlich

Siegfried Brunle

Rainer Nawrocki

Stuffing process for reducing waiting time jitter and device for

A circuit arrangement for imaging a useful digital signal from a frame of a first digital signal having a first bit rate into a frame of a second digital signal having a second bit rate, where the useful digital signal had been written into a first elastic memory and then read out of the first elastic memory in the frame of the first digital signal using a pulse stuffing technique, and with the frame of the first digital signal containing data representing the average fill level of the first elastic memory. The arrangement includes a second elastic memory, a frame detector for detecting the frame of the first signal and controlling activation of write-in of the useful digital signal from the frame of the first digital signal to the second elastic memory, and a frame generator which generates the frame of the second digital signal and controls activation of stuffing and of read-out of the useful digital signal from the second elastic memory into the frame of the second digital signal. An integrator determines the average fill level of the second elastic memory and a subtracter determines the difference between the average fill levels of the first and second elastic memories. This digital difference is fed to a digital control circuit, which includes a digital filter and a pulse density modulator that makes a stuffing decision as a function of the output of the digital filter. Each stuffing decision is input to the frame generator.

Arrangement for imaging a useful signal from the frame of a first

A method of recovering an original digital signal, after pulse stuffing, with reduced waiting time jitter. The original digital signal is written into a first elastic memory in a synchronizer. A pulse stuffed output of the synchronizer is transmitted to a desynchronizer where bits of the original signal are written into second elastic memory. Average values of fill levels of elastic memories in a synchronizer and in a desynchronizer are determined. The average value determined in the synchronizer is transmitted to the desynchronizer where a comparison of the respective average values is made in a comparator. A clock signal generating circuit in a phase locked loop is controlled by an output signal of the comparator so as to generate a clock signal. The signal bits written into the second elastic memory are read out of the second elastic memory at the rate of the generated clock signal.

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Munich, Georgia

Wolfgang Ehrlich