U.S. Philips Corporation

Wolfgang E Jasmer

Johann E Kruger

Ulrich R Killat

In broadband space-division switching networks a multi-layer p.c. board is used for wiring the switching matrices of adjacent switching stages. In case of a plurality of links between the switching matrices a corresponding number of layers of the p.c. board can be provided. The connection of the individual layers of the p.c. board requires much expenditure in point of manufacturing engineering. This expenditure can be reduced in a surprisingly simple manner, when a canonical linkage in a p.c. board is introduced such, that link sections of the switching matrix are fanned out into groups onto a layer of the p.c. board and combined again. By dividing the links into sections, requirements as regards equal line length, reduction of space required and replacement in case of defects can be met in a simple manner.

Broadband space-division switching network with linkage in a printed

In a switching system, more specifically a packet switching system, the flow control of the packets can be established by way of a datagram or by implementing the method of the virtual connection. For the optimization of the flow control the selected structure of the switching network is especially important. If the switching network is designed along the lines of a space-division multiplex switching network, each junction point of the bus bar system consisting of feeder lines and trunk lines has a comparator assigned thereto, which compares the addresses of the trunk lines arranged in columns with the routing information contained in the packet message headers. If, simultaneously, several of the auxiliary lines arranged in rows are to be connected through to one of the trunk lines arranged in a column, the order is determined by means of a decision circuit associated to each trunk line. If the order is determined by the spatial arrangement of the feeder lines, each decision circuit cyclically scans all comparators associated thereto, so that a new evaluation of the routing information is not achieved until the complete cycle has finished.

Method of and circuit arrangement for controlling a switching network in

Large-scale time-division switching arrangements often consist of a central switching network and a series of so-called concentrators. For establishing an H1 switching a series of wideband concentrators are connected to a central wideband switching network if the wideband concentrators are of a modular structure and communicate through an internal bus system and an interface circuit with the central wideband switching network connected thereto, a distribution switching in the direction of the subscriber station and a testing of the concentrators while in operation can be effected in a simple way.

Shared lines equipment, especially for B-ISDN switching system

A buffer memory for an input line of a digital interface serves to adapt input data which exhibit large phase fluctuations with respect to the local clock of the interface to this local clock. To this end it is necessary to write the input data with the associated clock into the buffer, the data being read with the local clock. Depending on the phase shifts, write and read operation are then liable to occur simultaneously in border cases. In order to enable the use of conventional components in spite of the described phenomenon, the buffer memory is composed of a number of storage blocks which each comprise the same number of addresses, the storage blocks normally being cyclically addressed in succession. An address spacing monitoring device ensures that read and write operations are always performed only in different storage blocks, so that they can take place simultaneously. When the spacing between read and write operations becomes less than the number of address positions of a storage block due to prolonged, large phase fluctuations so that there is a risk of simultaneous read and write operations within the same block, a read address jump is made in order to address a next or a preceding storage block so that the address is increased again. This address jump takes place only at or directly after the changing over of notably the read address from one storage block to another.

Buffer memory for an input line of a digital interface

A central exchange comprising at its input end a change-over arrangement having a change-over switch for each input line and at its output end a change-over arrangement of an identical structure having a change-over switch for each output line, which are controlled in parallel. Each change-over switch sequentially supplies at its output the channels of a multiplex frame on the different input lines. For each input line a data store and a control store are assigned to the change-over switch at the input end, in a predetermined sequence for each instant, each data store storing the words of all channels of always one input line, but always a different frame. Consequently, all the data stores together contain the words of all the input lines from a number of consecutive frames equal to the number of input lines. The control stores have the same number of addresses as the data store and address these addresses in a similar way, but always shifted through one frame length from data store to data store. This provides a switching matrix in which no blocking occurs and which behaves as a single-stage switching matrix, so that the switching path is controlled without path search.

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Hamburg, Germany

Wolfgang E Jasmer