Advanced Micro Devices Corporation

Globalfoundries Inc.

Wolfgang Buchholtz

Manfred Horstmann

Sven Beyer

Patrick Press

Petra Hetzer

Dmytro Chumakov

Andy C Wei

Karsten Wieczorek

Thorsten E Kammler

Markus Lenski

Thomas Feudel

Axel Preusse

Stephan Kruegel

Michael Raab

Markus Keil

Elvira Buchholtz

A capacitor is formed in nano channels in a conductive body. Embodiments include forming a source contact through a first inter layer dielectric (ILD), forming a conductive body on the first ILD, forming a second ILD on the conductive body, forming drain and gate contacts through the second ILD, conductive body, and first ILD, forming nano channels in the conductive body, forming an insulating layer in the channels, and metalizing the channels. An embodiment includes forming the nano channels by forming a mask on the second ILD, the mask having features with a pitch of 50 nanometers (nm) to 100 nm, etching the second ILD through the mask, etching the conductive body through the mask to a depth of 80% to 90% of the thickness of the conductive body, and removing the mask.

DRAM cell based on conductive nanochannel plate

By forming a substantially continuous and uniform semiconductor alloy in one active region while patterning the semiconductor alloy in a second active region so as to provide a base semiconductor material in a central portion thereof, different types of strain may be induced, while, after providing a corresponding cover layer of the base semiconductor material, well-established process techniques for forming the gate dielectric may be used. In some illustrative embodiments, a substantially self-aligned process is provided in which the gate electrode may be formed on the basis of layer, which has also been used for defining the central portion of the base semiconductor material of one of the active regions. Hence, by using a single semiconductor alloy, the performance of transistors of different conductivity types may be individually enhanced.

Semiconductor device comprising NMOS and PMOS transistors with embedded Si/Ge material for creating tensile and compressive strain

By forming an implantation mask prior to the definition of the drain and the source areas, an effective decoupling of the gate dopant concentration from that of the drain and source concentrations is achieved. Moreover, after removal of the implantation mask, the lateral dimension of the gate electrode may be defined by well-established sidewall spacer techniques, thereby providing a scaling advantage with respect to conventional approaches based on photolithography and anisotropic etching.

Field effect transistor having a doped gate electrode with reduced gate depletion and method of forming the transistor

By improving the purity of metal lines and the crystalline structure, the overall performance of metal lines, especially of highly scaled copper-based semiconductor devices, may be enhanced. The modification of the crystalline structure of the metal lines may be performed by a heat treatment generating locally restricted heating zones, which are scanned along the length direction of the metal lines, and/or a heat treatment comprising a heating step in a vacuum ambient followed by a heating step in a reducing ambient.

Technique for forming interconnect structures with reduced electro and stress migration and/or resistivity

Different types of crystalline semiconductor regions are provided on a single substrate by forming a dielectric region within a first crystalline semiconductor region. Thereafter, a second crystalline region is positioned above the dielectric region by wafer bond techniques. In preferred embodiments, isolation structures may be formed in the first crystalline region along with the dielectric region. In particular, crystalline semiconductor regions of different crystallographic orientations may be formed, wherein a high degree of flexibility and compatibility with currently used CMOS processes is maintained.

Technique for forming a substrate having crystalline semiconductor regions of different characteristics

A substrate comprising a first transistor element and a second transistor element is provided. A layer of a material is deposited over the first transistor element and the second transistor element. A portion of the layer of material is modified, which may be done, e.g., by irradiating the portion with ions or performing an isotropic etching process to reduce its thickness. An etching process adapted to remove the modified portion of the layer of material more quickly than an unmodified portion of the layer located over the second transistor element is performed.

Method of forming sidewall spacers

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Radebeul, Germany

Wolfgang Buchholtz