U.S. Philips Corporation

Semiconductor Ideas to Market (Itom) B.v.

Koninklijke Philips Corporation N.v.

Semiconductor Ideas to the Market (Itom) B.v.

Other

Semiconductor Ideas to Market, B.v.

Semiconductor Ideas to the Market

Semiconductors Ideas to Market B.v.

Semiconductors Ideas to Market (Itom) B.v.

Wolfdietrich G Kasperkovitz

Cicero Silveira Vaucher

Hendricus C De Ruyter

Wolter Bijker

Hendricus C De Ruijter

Willem A Sloof

Wolfgang Nolde

Herman W Van Rumpt

Dirk J Dullemond

Lukas Leyten

Kaveh Kianush

Winfried B Jansen

Johannes C Meeuwis

Abraham Jongepier

Arie Kuehn

Harry B Schoonheijm

Hubertus H Vereijken

Robert F Kokke

Nunziatina Mezzasalma

Hendricus C De Ruytere

Harry Barend Schoonheijm

Willem-Arie Sloof

A Class D amplifier comprising a control circuit configured to receive an audio input signal and derive first, second and third PWM switching control signals therefrom, being supplied to respectively first, second and third switches of a driver, the first and second switches being serially arranged between first and second supply voltages, and having a common node coupled to an output terminal. The driver comprises a DC level shifter being configured to provide a reference voltage to a reference terminal in at least first and second states of operation, said reference voltage including a DC component at least substantially equidistant between the first and second supply voltages. Said third switch being included in a shunt path between the output and the reference terminal.

Three level PWM class D amplifier

A class D amplifier output stage including an input for receiving an input signal, an output for providing an output signal to a load, serially coupled upper and lower switching devices configured to provide an output signal to the output, a driver circuit configured to receive the input signal, and to derive therefrom first and second drive signals for driving the upper and lower switching devices alternately from a conducting state into a non-conducting state and vice versa, such that the conducting state periods of the upper switching device with respect to those of the lower switching device are mutually exclusive and separated by dead time intervals during which both upper and lower output transistors are non-conducting. To reduce distortion and more particularly, total harmonic distortion (THD), the amplifier output stage includes a substantially linear circuit configured to provide a bidirectional current sink for residual currents from the load occurring during at least part of each dead time interval.

Class D amplifier

An anti-jamming system includes a tunable negative jamming signal feedback loop for feedback suppression of a received jamming signal. The system includes a zero IF phase locked loop (PLL) jamming signal receiver having a synchronous demodulator and a phase detector. A VCO is included in the PLL, as well as a phase detector and a loop filter. A replica jamming signal generator includes a tracking modulator with a baseband signal input coupled to an output of a synchronous demodulator in the receiver and a carrier input provided by the VCO. An output of the tracking modulator is negatively fed back to the input of the receiver to suppress the jamming signal in the received input.

Anti-jamming system

FM receiver including an RF input circuit followed by a tunable mixer stage for frequency conversion of an RF FM signal into an IF FM signal, which is coupled to an FM input of a first narrow-band IF filter. The center frequency of the first narrow-band IF filter is controlled to vary in dependence on the IF FM signal. The first narrow-band IF filter is subsequently coupled to a first FM demodulator and a first LF signal processing unit. To increase the receiver's selectivity and sensitivity without adversely affecting tracking stability, the FM input of a first narrow-band IF filter is coupled through a second FM demodulator to a control input of said first narrow-band FM tracking filter for a feed forward tracking control of the center frequency of said first narrow-band FM tracking filter with the momentary frequency of the IF FM signal.

FM receiver

Anti jamming system comprising a tunable negative jamming signal feedback loop for feedback suppression of a received jamming signal, including an receiver receiving an jamming signal followed by a replica jamming signal generator for generating an replica jamming signal. The receiver comprising a zero IF PLL receiver having a synchronous demodulator and a phase detector, signal inputs thereof being coupled to said input means and carrier inputs coupled to in-phase and phase quadrature oscillator outputs, respectively, of a local voltage controlled oscillator (VCO), said VCO receiving a tuning control signal for tuning the zero IF PLL receiver at the carrier frequency of the jamming signal. The VCO is included in a phase locked loop (PLL) comprising subsequent to the VCO, said phase detector and a loop filter. The replica jamming signal generator includes a modulator with a baseband signal input coupled to an output of said synchronous demodulator and a carrier input coupled to the in-phase oscillator output of the VCO, an output of said modulator being negatively fedback to the input of the receiver.

Anti jamming system

Anti jamming system comprising a tunable negative jamming signal feedback loop for feedback suppression of a received jamming signal, including a receiver receiving an jamming signal followed by a jamming signal replica generator for generating an replica jamming signal. The receiver comprising a zero IF PLL jamming signal receiver having a synchronous demodulator and a phase detector, signal inputs thereof being coupled to said input means and carrier inputs coupled to in-phase and phase quadrature oscillator outputs, respectively, of a local voltage controlled oscillator (VCO), said VCO receiving a tuning control signal for tuning the zero IF PLL jamming signal receiver at the carrier frequency of the jamming signal. The VCO is included in a phase locked loop (PLL) comprising subsequent to the VCO, said phase detector and a loop filter. The replica jamming signal generator includes a tracking modulator with a baseband signal input coupled to an output of said synchronous demodulator and a carrier input coupled to the in-phase oscillator output of the VCO, an output of said modulator being negatively fedback to the input of the receiver.

Controllable operational transconductance power amplifier (controllable power OTA) including an input stage receiving a differential input signal (Ovin) and deriving therefrom first (i) and second (i) low power current signals being coupled to first (ccs) and second (ccs) current controlled output current sources being arranged in class B push pull configuration. To obtain an effective gain control while securing power efficiency and linearity, the overall gain of the power OTA is controlled by varying the gain or transconductance of the input stage (c) and by the use of means for bi-directionally rectifying said first (i) and second (io) low power current signals and providing in mutual alternation power amplification of said first (i) and second (i) low power current signals into first (I) and second (Io) mutually exclusive high power current output signals, which are supplied through a current summer to a current output (I) of said linear power amplifier.

Controllable power operational transconductance amplifier

An integrated RC filter comprises a first resistor being coupled to a first capacitor through a first node and a signal input of said integrated RC filter is coupled through one of the first resistor and the first capacitor to the first node. To allow for an increase in the RC time constant of the RC filter without losing signal transparency, amplification means are included between said signal input and said one of the first resistor and the first capacitor having a gain factor substantially larger than unity, said first node being coupled through attenuation means to a signal output, said attenuation means having an attenuation factor substantially.

Integrated RC filter

Multiplier device comprising first to nmultipliers Mto Mfor multiplying a carrier modulated information signal with first to nmutually phase shifted and identical, substantially square wave mixing signals MSto MSwith 50% duty cycle. In order to eliminate fifth or higher order interferences from the output of said multiplier device according to the invention, n is greater than 2, outputs of said multipliers Mto Mare respectively coupled through weighting circuits Wto Wwith respective fixed weighting factors WFto WFto an adder circuit, said mixing signals MSto MShaving respective phase angles &#x3c6;corresponding to &#x3c6;=i*&#x394;&#x3c6;, said weighting factors WFcorresponding to the sine value of said respective phase angles &#x3c6;=i*&#x394;&#x3c6; with &#x394;&#x3c6; being the mutual phase difference between each two phase consecutive mixing signals corresponding to &#x3c0;/(n+1) and i varying from 1 to n.

Multiplier device

Tunable low noise amplifier using an RF current feed back loop (L) coupled between input (IM) and output (OM) means and including first (CAI) and second (CA) serially coupled first order lowpass RF current amplifiers as well RF current inverter means (INV). To obtain narrow bandpass selectivity within a relatively wide tuning range e.g. from 40 MHz to 1000 MHz said first RF current amplifier is being provided with a current gain larger than that of the second RF current amplifier, and a 3 dB cut off frequency lower than the 3 dB cut off frequency of said second RF current amplifier, a tuning control signal being supplied to both first and second RF current amplifiers to vary the respective 3 dB cut off frequencies thereof.

Tunable low noise amplifier

Control system for programmable filters, master-slave calibration system and fully programmable high precision filter for use in such control system, such filters being provided with a filter input and a filter output including a first, first order low pass filter section comprising first and second mutually identical operational transconductance amplifiers (OTAs), having a controllable transconductance Gm from a differential voltage input having first and second differential voltage input terminals to a single current output carrying a single phase current output signals, said first and second OTAs being provided with first and second control inputs, respectively, said filter input being coupled to the first differential voltage input terminal of said first OTA. The current outputs of both first and second OTAs are being resistorless coupled to a first capacitor, the current output of the second OTA is negatively fed back to its first differential voltage input terminal to form a variable positive virtual resistance across said first capacitor, the common connection of the single current outputs of the first and second OTAs and the first capacitor constituting an output terminal of the first, first order low pass filter section, which is coupled to said filter output, the second differential voltage input terminals of the first and second OTAs being respectively coupled to first and second DC reference voltage levels, a gain and a bandwidth control signal being respectively supplied to the first and second control input terminals of said first and second OTA. To obtain an unambiguous and orthogonal control of filter parameters, such as gain, bandwidth, quality factor and/or tuning frequency, said gain control signal is provided through a first multiplier to said first control input terminal of the first, first order low pass filter section for multiplying the gain control signal with said bandwidth control signal and said bandwidth control signal at least to said second control input terminal of the first, first order low pass filter section.

Control system for programmable filters

A mirror suppression circuit includes a first quadrature signal path coupled between quadrature signal input and output terminals and an error correction circuit for correction of amplitude and phase errors in a carrier modulated quadrature signal. To obtain a suppression of both amplitude and phase imbalance of the carrier modulated quadrature signal as well as signal amplitude variations, a quadrature output of the error correction circuit is coupled to an error detection circuit. The error detection circuit detects amplitude and phase errors and provides amplitude and phase control signals to the error correction circuit for a negative feed back of the amplitude and phase errors. The amplitude and phase control signals vary with products of components of the quadrature signal and components of a quadrature reference signal.

Mirror suppression circuit and receiver using such circuit

Receiver comprising an RF front end circuit for a selection and conversion of an RF input signal into a pair of quadrature IF (intermediate frequency) signals being supplied through in-phase and phase quadrature signal paths to signal inputs of quadrature phase detection elements, such as in-phase and phase quadrature phase detectors included in a (PLL) phase locked loop, an output of the quadrature phase detection elements being coupled through a loop filter to a control input of a quadrature IF oscillator supplying a pair of quadrature IF oscillator signals to carrier inputs of the quadrature phase detection elements. To suppress amplitude and phase mismatch deteriorating proper mirror cancellation the quadrature phase detection elements is coupled to amplitude and phase error signal for a detection of amplitude and phase errors in the output signal of the quadrature phase detection elements and a quadrature frequency doubler is coupled between the quadrature local oscillator and carrier inputs of the amplitude and phase error detection means to supply respectively thereto in-phase and phase quadrature error detection carrier signals at twice the IF carrier frequency of the pair of quadrature IF signals, the amplitude and phase error detection means respectively providing amplitude and phase error signals through first and second low-pass filters to an amplitude correction circuit and a phase correction circuit preceding at least one of the inputs of the quadrature phase detection elements for a negative feedback of the amplitude and phase errors.

Receiver with mirror frequency suppression

AM receiver comprising an RF input circuit for receiving an RF AM signal, demodulation means providing an audio signal carried by said RF AM signal as well as automatic gain control means for stabilising an RF carrier dependent DC level at the output of said demodulation means at a substantially fixed stabilisation value. In order to improve the receiver performance in particular at low values of the RF reception fieldstrength, the RF input circuit is being provided with a cascade of N tuneable resonance amplifiers being tuned to said RF AM signal, said automatic gain control means controlling at least one of said cascade of N resonance amplifiers to increase in both gain and selectivity at a decrease of the fieldstrength of said RF input signal.

AM receiver with controllable RF input circuit

An arrangement for decoding a stereo multiplex signal, comprising a baseband sum signal (L+R), a difference signal (L&#x2212;R) which is amplitude-modulated on a suppressed sub-carrier and a pilot signal having a frequency located between the frequency bands of said sum and difference signals, said arrangement having an input for the stereo multiplex signal coupled through parallel stereo sum and difference signal paths to first and second inputs of a dematrix circuit, a synchronous demodulator being included in the difference signal path, a local sinusoidal sub-carrier being supplied to a carrier input of said synchronous demodulator for a synchronous demodulation of said amplitude-modulated difference signal (L&#x2212;R) into baseband. To maximize stereo channel separation the arrangement is provided with an automatic gain control loop comprising a first mixer stage receiving a reference signal, a signal output thereof being coupled to a second mixer stage, both mixer stages having carrier inputs being supplied with said local sinusoidal sub-carrier for a respective up and down conversion of said reference signal, a signal output of said second mixer stage being coupled through a 6 dB attenuator to a difference circuit providing the difference between the output signal of the attenuator and the reference signal, said difference circuit being coupled to a control input of gain controlled amplifying means for varying the gain of said synchronous demodulator and said first and second mixer stages.

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Eindhoven, Netherlands

Wolfdietrich G Kasperkovitz