International Business Machines Corporation

Wolfdieter Lohlein

Minh H Tong

Klaus Helwig

Jorg Gschwendtner

A decoding process and a decoding circuit arrangement for a redundant semiconductor memory is described, wherein the advantages of parallelly selecting non-defective word lines and redundant word lines at a low level are utilized for the writing as well as for the reading current in such a manner that high speed reading and writing is not affected. This is achieved in that the decoder for the redundant word lines consists of a comparator circuit and fuse-controlled switches, and that the input addresses are applied to a conventional address decoder as well as to the comparator circuit. The output of the comparator circuit is directly connected to the input of a first driver circuit for the redundant word line, and furthermore to an OR circuit which is also controlled by a read/write control circuit, and which is connected to the decoder and to a clamp circuit that is directly connected to the input of a second word line driver circuit, and continuously maintains the potential following a deselect signal applied on that level, which requires a minimum of power.

Decoding circuit arrangement for redundant semiconductor storage systems

A known FET driver circuit which is to be controlled at the gate by means of relatively low TTL signals, is improved in such a manner that the source potential of the input transistors is shifted oppositely to the input signal. This leads to an increase in the effective potential difference in the signal level applied to the input transistors and thus to an improved switching speed.

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Herrenberg, Germany

Wolfdieter Lohlein