Nvidia Corporation

Wojciech Jan Truty

Samuel Hammond Duncan

Philip Browning Johnson

Lincoln G Garlick

Gary Ward

Jesse Max Guss

M Wasiur Rashid

Chris Marriott

A multi-threaded processing unit includes a hardware pre-processor coupled to one or more processing engines (e.g., copy engines, GPCs, etc.) that implement pre-emption techniques by dividing tasks into smaller subtasks and scheduling subtasks on the processing engines based on the priority of the tasks. By limiting the size of the subtasks, higher priority tasks may be executed quickly without switching the context state of the processing engine. Tasks may be subdivided based on a threshold size or by taking into account other consideration such as physical boundaries of the memory system.

Technique for improving performance in multi-threaded processing units

One embodiment of the present invention includes a hard-coded first device ID. The embodiment also includes a set of fuses that represents a second device ID. The hard-coded device ID and the set of fuses each designate a separate device ID for the device, and each device ID corresponds to a specific operating configuration of the device. The embodiment also includes selection logic to select between the hardcoded device ID and the set of fuses to set the device ID for the device. One advantage of the disclosed embodiments is providing flexibility for engineers who develop the devices while also reducing the likelihood that a third party can counterfeit the device.

Setting a PCIE Device ID

Growing community of inventors

Redwood City, CA, United States of America

Wojciech Jan Truty