Bae Systems Information and Electronic Systems Integration Inc.

Frantorf Investments Gmbh, LLC

Wojciech J Krawiec

Kevin S Bassett

Michael J Kotrlik

John M Smith

The system can utilize a standard high speed FPGA interface for a non-traditional use to facilitate the processing of high amounts of streaming digital data or the method can be implemented in other high speed data transfer systems. This system and method include the use of training/calibration pattern techniques implemented in a FPGA, or other system, to calibrate numerous multi-arm demultiplexers. The training/calibration sequence data rate being slower than the input data rate. In one example, the system and method utilized a mono-bit receiver capable of digitizing signals of at least 40 GHz with at least 20 GHz of instantaneous bandwidth.

High speed data transfer

A two-plane rotation (TPR) approach to Gaussian elimination (Jacobi) is used for computational efficiency in determining rotation parameters. A rotation processor is constructed using the TPR approach to perform singular value decomposition (SVD) on two by two matrices yielding both eigenvalues and left and right eigenvectors. The rotation processor can then be replicated and interconnected to achieve higher dimensioned matrices. For higher dimensional matrices, the rotation processors on the diagonal solve the 2&#xd7;2 rotation angles, broadcast the results to off-diagonal processors, whereby all processors perform matrix rotations in parallel.

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Amherst, NH, United States of America

Wojciech J Krawiec