Environmental Research Institute of Michigan

Wlodzimierz Holsztynski

Stephen S Wilson

A system particularly suited for serially processing spatially oriented data such as data matrices includes a plurality of serially connected processing cells for performing a number of successive, different operations on the data using pipeline processing techniques. In one embodiment, each unit cell comprises a memory in the form of a shift register for storing data received from the neighboring, upstream cell. The data is transferred from the memory to a time delaying storage medium such as a latch and to a processing circuit which operates on the data and provides data output to the neighboring, downstream cell. In another embodiment, a simple parallel-in, parallel-out latch is employed as the cell memory thereby allowing the processing circuit to simultaneously access all of the data stored in memory. Data is output from the latch in pre-determined groups and is multiplexed to one portion of the processing circuit. One of the data groups output from the latch is delayed by a shift register and then delivered to another portion of the processing circuit which selectively receives data from the first portion. A central controller connected to each cell controls the transfer of data within and between the cells.

Pipeline processor

A rectangular digital logic array for performing transformations on data matrices for solving wave equations, image processing problems and the like, includes a plurality of identical cells each having a processing element which receives one of its inputs from a single bit accumulator and provides its output to a similar single bit accumulator. The input accumulators of each row in the array are formed by a single parallel input, parallel output shift register and the output accumulators of each column in the array are similarly formed by a parallel input, parallel output shift register. The shift registers operate to connect each cell except those at the edge of the array with two neighboring cells along one axis and two neighboring cells along the orthogonal axis. Four edge shift registers bordering the array allow data to be transferred into and out of the cells and a central processor connected to each of the cells controls the sequence of cell operations and the transfer of data between cells for all cells simultaneously. The simple cell and interconnection structure allows the economical formation of large arrays so that very high processing speeds may be achieved despite the multiple processing steps which each elemental cell must undergo in order to perform a complex computation.

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Ann Arbor, MI, United States of America

Wlodzimierz Holsztynski