Oracle America, Inc.

Oracle International Corporation

Sun Microsystems, Inc.

Wladyslaw Olesinski

Hans Eberle

Nils Gura

Sumti Jairath

Robert Dickson

Aron J Silverton

Peter J Yakutis

Robert J Drost

Robert David Hopkins

Georgios A Passas

Andreas Mejia

Embodiments of a system that includes a switch and a buffer-management technique for storing signals in the system are described. In this system, data cells are dynamically assigned from a host buffer to at least a subset of switch-ingress buffers in the switch based at least in part on the occupancy of the switch-ingress buffers. This buffer-management technique may reduce the number of switch-ingress buffers relative to the number of input and output ports to the switch, which in turn may overcome the limitations posed by the amount of memory available on chips, thereby facilitating large switches.

Dynamic assignment of data to switch-ingress buffers

A method for managing packets, including: identifying a first plurality of packets from a first packet source having a first weight; identifying a second plurality of packets from a second packet source having a second weight; obtaining a first weight ratio based on the first weight and the second weight; obtaining an error threshold and a first error value corresponding to the second packet source, where the error threshold exceeds the first error value; forwarding a first packet from the first packet source in response to the error threshold exceeding the first error value; incrementing the first error value by the first weight ratio; forwarding a first packet from the second packet source, after incrementing the first error value and in response to the first error value exceeding the error threshold; and decrementing the first error value.

Weighted differential scheduler

A method includes a local switch receiving a first set of upstream packets and a first set of local packets, each assigned a first class of service. The local switch inserts, according to a first insertion rate, a local packet between subsets of the first set of upstream packets to obtain an ordered set of first class packets. The local switch also receives a second set of upstream packets and a second set of local packets, each assigned a second class. The local switch inserts, according to a second insertion rate, a local packet between subsets of the second set of upstream packets to obtain an ordered set of second class packets. The method includes for each timeslot, selecting a class, and forwarding a packet from the selected class of service to a downstream switch. The switches are interconnected in a daisy chain topology on a single chip.

Classes of service for network on chips

A method for transmitting packets, including forwarding a first set of upstream packets and a first set of local packets by inserting at least one of the first set of local packets between subsets of the first set of upstream packets according to a first insertion rate; calculating a second insertion rate after forwarding a predetermined number of upstream packets generated by a single upstream source, by dividing a cardinality of the first set of upstream packets by a greatest common divisor of the predetermined number and the cardinality of the first set of upstream packets; and forwarding a second set of upstream packets and a second set of local packets from the local switch to the downstream switch by inserting at least one of the second set of local packets between subsets of the second set of upstream packets according to the second insertion rate.

Simple fairness protocols for daisy chain interconnects

A method for managing packets, including identifying a first packet source having a first weight and second packet source having a second weight, where the first weight exceeds the second weight; assembling a first regular subsequence of packets using a first packet from the second packet source and a first set of packets from the first packet source having a cardinality equal to a first weight ratio; assembling a first augmented subsequence of packets using a second packet from the second packet source and a second set of packets from the first packet source having a cardinality equal to the first weight ratio plus one; and forwarding a first sequence of packets including a first set of regular subsequences, which includes the first regular subsequence, and a first set of augmented subsequences, which includes the first augmented subsequence and has a cardinality based on the first augmented subsequence factor.

Simple low-jitter scheduler

Embodiments of the present invention provide a system that schedules the transfer of cells in a switch. The system starts by receiving a set of cells to be transferred from a set of inputs of the switch to a set of outputs of the switch. The system includes S subschedulers, wherein each subscheduler processes N scheduling waves in sequence to generate a conflict-free transfer schedule for a given time slot for a matrix of transfer elements in the switch. The system then operates the subschedulers in parallel to generate S transfer schedules to transfer the cells from the set of inputs of the switch to the set of outputs of the switch during S time slots.

Parallel wrapped wave-front arbiter

Embodiments of the present invention provide a system that transfers data between the components in the computer system through a switch. In these embodiments, the switch includes multiple switch chips which are coupled together and are configured to collectively function as a switch. During operation, each switch chip, receives cells from the subset of the set of inputs and selectively transfers each of the cells to at least one output of the subset of the set of outputs coupled to the switch chip or of the subset of the set of outputs coupled to the other switch chips.

Architecture for an output buffered switch with input groups

Embodiments of a circuit, a buffered crosspoint switch that includes the circuit and a computer system that includes the switch are described. In this circuit and switch, deep crosspoint buffers are replaced with smaller distributed buffers. This modification reduces the cost of the switch and improves the scaling properties of the architecture.

Fast and fair arbitration on a data link

Embodiments of a scheduler for a switch, where the switch is configured to couple input ports to output ports are described. During operation, the scheduler may determine a schedule based on a group of requests, associated with multiple data streams, that are received for the output ports of the switch, where the schedule matches input ports to output ports of the switch for a given data cell time. Note that the schedule may be determined using an arbitration technique during a time interval. Moreover, the scheduler may assign an additional request, which was received at a time that precedes a current time by less than the time interval, to a portion of the switch which is available in the schedule, thereby reducing a latency of the scheduler.

Low-latency scheduling in large switches

A system that includes a first buffer and a second buffer, wherein the first buffer and the second buffer are connected to the same input, wherein a size of the first buffer is defined by a distance of the first buffer from the input and a transfer rate of data, wherein a size of the second buffer is defined by a distance of the second buffer from the input and the transfer rate of data, and wherein the distance between the first buffer and the input is different from the distance between the second buffer and the input.

Method and system for sizing flow control buffers

A switch contains a first semiconductor die, which is configured to receive signals on a plurality of input ports and to output the signals on a plurality of output ports. The first semiconductor die is further configured to selectively couple the signals between the input and output ports using a plurality of switching elements in accordance with a set of control signals, which correspond to a configuration of the switch. During this process, a plurality of proximity connectors, proximate to a surface of the semiconductor die, are configured to communicate the signals by capacitive coupling.

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Pleasanton, CA, United States of America

Wladyslaw Olesinski