Yozan Corporation

Sharp Corporation

Wiwat Wongwarawipat

Makoto Yamamoto

Weikang Yang

Sunao Takatori

Guoliang Shou

Guoliang Shu

A circuit for weighted addition which includes a transistor having a gate and a plurality of resistance elements. Each resistance element has a first and second end. The first end of each resistance element is impressed with a voltage, and the second end of each resistance element is connected to the gate of the transistor. The circuit is small in size and renders precise and various types of weighted addition possible.

Circuit for weighted addition

A circuit calculating the minimum value comprising a plural number of pMOS, wherein source of the plural pMOS are connected to a power source with lower voltage than a drain, the drain is grounded through high resistance, in input voltage is connected to each pMOS, and a common output is connected to a drain of each pMOS.

Circuit for calculating the minimum value

A calculating circuit for outputting a maximum value based on a plurality of inputs. The circuit is comprised of a plurality of nMOS transistors connected in a parallel configuration.

Circuit for calculating a maximum value

An analog calculation circuit has a circuit input for receiving a first input voltage, a circuit output, a first timer, and a second timer. The first timer has a first capacitive coupler, a first RC circuit, and a first threshold circuit for outputting a first timer output voltage. The first threshold circuit has a first threshold input terminal. The first capacitive coupler has a first capacitive coupler input connected to the circuit input, a second capacitive coupler input, and a first capacitive coupler output connected to the first threshold input terminal. The first RC circuit has a first resistance, a first capacitance, a first RC input for receiving a second input voltage, and a first RC output connected to the second capacitive coupler input. The second timer has a second RC circuit, a second threshold circuit for outputting a second timer output voltage to the second RC circuit, and for receiving the first timer output voltage. The second RC circuit has a second resistance, a second capacitance, a second RC input for receiving a third input voltage, and a second RC output connected to the circuit output. A third timer, similar in design to the first timer may also be used in the calculation circuit.

Analog calculation circuit using timers

A voltage follower circuit comprising an nMOS transistor whose drain is connected to a power source and a pMOS transistor whose drain is connected to the source of the nMOS transistor and whose source is grounded, wherein input voltage is connected to the gates of nMOS and pMOS transistor. A source of the nMOS transistor is connected to an output terminal, and the output terminal is grounded through capacitance.

Growing community of inventors

Tokyo, Japan

Wiwat Wongwarawipat