Micron Technology Incorporated

Headway Technologies, Incorporated

Magic Technologies, Inc.

Hitachi Global Storage Technologies Netherlands B.v.

Silicon Magnetic Systems

International Business Machines Corporation

Centre National De La Recherche Scientifique

Cypress Semiconductor Corporation

Antaios

Witold Kula

Gurtej S Sandhu

Ru-Ying Tong

Cheng Tzong Horng

Guenole Jan

Chyu-Jiuh Torng

Manzar Siddik

Wayne I Kinney

Wei Chen

Ru Ying Tong

Wei Cao

Yu-Jen Wang

Stephen J Kramer

Rongfu Xiao

Sunil S Murthy

Yu Jen Wang

Tom Zhong

Alexander Michael Zeltser

Jonathan D Harms

Suresh Ramarajan

Robert Beach

Andy Lyle

John A Smythe

Liubo Hong

Wai-Ming Johnson Kan

Chyu Jiuh Torng

Terry Kin Ting Ko

Chyu-Jinh Torng

Po-Kang Wang

Eugene Youjun Chen

Tai Min

Kamel Ounadjela

Guangli Liu

Rodolfo Belen

Sam G Geha

Jean-Pierre Nozieres

Francois H Fabreguette

Gilles Louis Gaudin

Benjamin C E Schwarz

Chang Ju Choi

Marc Drouard

Biju Parameshwaran

Helen L Chung

Ruth Tong

Chyu-Jiuh Tomg

Tom Zhang

Adam Zhang

Johnathan D Harms

Jerome S Wolfman

A magnetic cell core includes a seed region with a plurality of magnetic regions and a plurality of nonmagnetic regions thereover. The seed region provides a template that enables formation of an overlying nonmagnetic region with a microstructure that enables formation of an overlying free region with a desired crystal structure. The free region is disposed between two nonmagnetic regions, which may both be configured to induce surface/interface magnetic anisotropy. The structure is therefore configured to have a high magnetic anisotropy strength, a high energy barrier ratio, high tunnel magnetoresistance, a low programming current, low cell-to-cell electrical resistance variation, and low cell-to-cell variation in magnetic properties. Methods of fabrication, memory arrays, memory systems, and electronic systems are also disclosed.

Electronic devices including a seed region and magnetic regions

A transistor comprising a channel region on a material is disclosed. The channel region comprises a two-dimensional material comprising opposing sidewalls and oriented perpendicular to the material. A gate dielectric is on the two-dimensional material and gates are on the gate dielectric. Semiconductor devices and systems including at least one transistor are disclosed, as well as methods of forming a semiconductor device.

Transistors comprising two-dimensional materials and related memory cells and electronic devices

Electronic devices with seed and magnetic regions and methods of fabrication

A magnetic memory (MRAM) cell, comprising: a first layer formed from a substantially electrically conductive material; and a magnetic tunnel junction (MTJ) stack formed over the first layer, wherein the MTJ stack comprises: a ferromagnetic reference layer having an in-plane reference magnetization; a tunnel barrier layer; and a ferromagnetic storage layer between the tunnel barrier layer and the first layer, the storage layer having an in-plane storage magnetization; wherein the MTJ stack comprises an arrangement for providing an in-plane uniaxial anisotropy in the storage layer; wherein said in-plane uniaxial anisotropy makes an angle with the direction of the write current that is between 5&#xb0; and 90&#xb0;, and wherein said in-plane uniaxial anisotropy has an energy between 40 and 200 kBT and wherein coercivity is larger than 200 Oe.

Magnetic memory cell having deterministic switching and high data retention

A magnetic cell includes a free region between an intermediate oxide region (e.g., a tunnel barrier) and a secondary oxide region. Both oxide regions may be configured to induce magnetic anisotropy ('MA') with the free region, enhancing the MA strength of the free region. A getter material proximate to the secondary oxide region is formulated and configured to remove oxygen from the secondary oxide region, reducing an oxygen concentration and an electrical resistance of the secondary oxide region. Thus, the secondary oxide region contributes only minimally to the electrical resistance of the cell core. Embodiments of the present disclosure therefore enable a high effective magnetoresistance, low resistance area product, and low programming voltage along with the enhanced MA strength. Methods of fabrication, memory arrays, memory systems, and electronic systems are also disclosed.

Electronic systems including magnetic regions

Memory cells are disclosed. Magnetic regions within the memory cells include an alternating structure of magnetic sub-regions and coupler sub-regions. The coupler material of the coupler sub-regions antiferromagnetically couples neighboring magnetic sub-regions and effects or encourages a vertical magnetic orientation exhibited by the neighboring magnetic sub-regions. Neighboring magnetic sub-regions, spaced from one another by a coupler sub-region, exhibit oppositely directed magnetic orientations. The magnetic and coupler sub-regions may each be of a thickness tailored to form the magnetic region in a compact structure. Interference between magnetic dipole fields emitted from the magnetic region on switching of a free region in the memory cell may be reduced or eliminated. Also disclosed are semiconductor device structures, spin torque transfer magnetic random-access memory (STT-MRAM) systems, and methods of fabrication.

Magnetic structures, semiconductor structures, and semiconductor devices

Transistors comprising two-dimensional materials and related semiconductor devices, systems, and methods

A method of doping a silicon-containing material. The method comprises forming at least one opening in a silicon-containing material and conformally forming a doped germanium material in the at least one opening and adjacent to the silicon-containing material. A dopant of the doped germanium material is transferred into the silicon-containing material. Methods of forming a semiconductor device are also disclosed, as are semiconductor devices comprising a doped silicon-containing material.

Methods of doping a silicon-containing material and methods of forming a semiconductor device

A magnetic tunnel junction comprises a conductive first magnetic electrode comprising magnetic recording material, a conductive second magnetic electrode spaced from the first electrode and comprising magnetic reference material, and a non-magnetic tunnel insulator material between the first and second electrodes. The magnetic reference material of the second electrode comprises a synthetic antiferromagnetic construction comprising two spaced magnetic regions one of which is closer to the tunnel insulator material than is the other. The one magnetic region comprises a polarizer region comprising CoFeBwhere 'x' is from 0 to 90, 'y' is from 10 to 90, and &#x201c;z&#x201d; is from 10 to 50. The CoFeBis directly against the tunnel insulator. A non-magnetic region comprising an Os-containing material is between the two spaced magnetic regions. The other magnetic region comprises a magnetic Co-containing material. Other embodiments are disclosed.

Magnetic tunnel junctions

Magnetic memory cells, methods of fabrication, semiconductor device structures, and memory systems are disclosed. A magnetic cell core includes at least one magnetic region (e.g., a free region or a fixed region) configured to exhibit a vertical magnetic orientation, at least one oxide-based region, which may be a tunnel junction region or an oxide capping region, and at least one magnetic interface region, which may comprise or consist of iron (Fe). In some embodiments, the magnetic interface region is spaced from at least one oxide-based region by a magnetic region. The presence of the magnetic interface region enhances the perpendicular magnetic anisotropy (PMA) strength of the magnetic cell core. In some embodiments, the PMA strength may be enhanced more than 50% compared to that of the same magnetic cell core structure lacking the magnetic interface region.

Electronic devices and related electronic systems

Semiconductor devices with seed and magnetic regions and methods of fabrication

A magnetic cell core includes at least one stressor structure proximate to a magnetic region (e.g., a free region or a fixed region). The magnetic region may be formed of a magnetic material exhibiting magnetostriction. During switching, the stressor structure may be subjected to a programming current passing through the magnetic cell core. In response to the current, the stressor structure may alter in size. Due to the size change, the stressor structure may exert a stress upon the magnetic region and, thereby, alter its magnetic anisotropy. In some embodiments, the MA strength of the magnetic region may be lowered during switching so that a lower programming current may be used to switch the magnetic orientation of the free region. In some embodiments, multiple stressor structures may be included in the magnetic cell core. Methods of fabrication and operation and related device structures and systems are also disclosed.

Semiconductor devices with magnetic regions and stressor structures

A magnetic cell includes a magnetic region formed from a precursor magnetic material. The precursor magnetic material included a diffusible species and at least one other species. An oxide region is disposed between the magnetic region and another magnetic region, and an amorphous region is proximate to the magnetic region. The amorphous region includes an attracter material that has a chemical affinity for the diffusible species that is higher than a chemical affinity of the at least one other species for the diffusible species. Thus, the diffusible species is transferred from the precursor magnetic material to the attracter material, forming a depleted magnetic material. The removal of the diffusible species and the amorphous nature of the region of the attracter material promotes crystallization of the depleted magnetic material, which enables high tunnel magnetoresistance and high magnetic anisotropy strength. Methods of fabrication and semiconductor devices are also disclosed.

Memory cells, methods of fabrication, and memory devices

A semiconductor device comprises an array of magnetic cell structures each comprising a magnetic tunnel junction over an electrode on a substrate. Each of the magnetic tunnel junctions includes a magnetic material over the substrate, a first tunnel barrier material over the magnetic material, a second tunnel barrier material over the annealed first tunnel barrier material, and another magnetic material over the second tunnel barrier material. Each magnetic tunnel junction is configured to exhibit a tunnel magnetoresistance greater than or equal to about 180% at a resistance area product of less than about 8 ohm &#x3bc;m. The semiconductor device also includes another electrode over the another magnetic material. Semiconductor devices including the magnetic tunnel junctions, methods of forming the magnetic tunnel junctions, and methods of forming semiconductor devices including the magnetic tunnel junctions are disclosed.

Methods of forming semiconductor devices including tunnel barrier materials

Growing community of inventors

Gilroy, CA, United States of America

Witold Kula