Infineon Technologies Ag

Witold Gora

Albrecht Mayer

Gerd Dirscherl

Ljudmil Anastasov

Bejoy Mathews

Thomas Langschwert

Andreas Geiler

Peter Blicharski

Leong Kee Chee

A radar system may include a set of analog components to perform one or more radio frequency (RF) operations during an active radar phase of the radar system. The radar system may include a set of digital components to perform one or more digital processing operations during at least a digital processing phase of the radar system. The one or more digital processing operations may be performed such that performance of the one or more digital processing operations does not overlap performance of a substantive portion of the one or more RF operations.

On-chip noise reduction and power consumption distribution for a radar system

A circuit for detecting a signal disturbance comprising a high-pass filter, a comparator, an asynchronous counter, a synchronizer, and processing circuitry. The high-pass filter is configured to generate a filtered signal from a monitored signal. The comparator is configured to generate a compare result signal based on a comparison of the filtered signal and a threshold reference. The asynchronous counter is configured to generate a count value of threshold crossings based on the compare result signal. The synchronizer is configured to generate a synchronous output signal for storage at digital memory that is based on the count signal value. The processing circuitry is configured to determine that a disturbance has occurred at the monitored signal based on the synchronous output signal.

Detecting signal disturbance using asynchronous counter

According to one embodiment, a data processing device is described including a non-volatile memory configured to store configuration data for the data processing device, a volatile memory and a control system configured to copy the configuration data from the non-volatile memory to a section of the volatile memory, block writing to the section of the volatile memory and to put the data processing device into a hibernation mode in which the non-volatile memory is inactive and the volatile memory is active.

Data processing device and method for saving power in a data processing device

An apparatus and corresponding method for preventing cloning of code. The apparatus includes a memory, an authentication module, and a device. The memory is configured to store the code, which includes unencrypted code and a fragment of encrypted code. The authentication module is configured to receive and decrypt the fragment of encrypted code from the memory into a fragment of decrypted code, and to store the fragment of decrypted code in an authentication module buffer. The device configured to execute the unencrypted code from the memory and to execute the fragment of decrypted code from the authentication module buffer, wherein the fragment of encrypted code is personalized to the device.

Growing community of inventors

Unterhaching, Germany

Witold Gora