Taiwan Semiconductor Manufacturing Comp. Ltd.

Winston Shue

Mong-Song Liang

Shih-Wei Chou

Jing-Cheng Lin

Ming-Hsing Tsai

Cheng-Lin Huang

Minghsing Tsai

Chi-Wei Chang

Maureen Wang

Cheng Lin Huang

A new method is provided that allows for the application of electropolish for removal of copper and that is independent of pattern density of the removed copper. Electropolish of the copper is first accomplished by reversing current in the HSOor HPOsolution. After identifying the endpoint of the electropolish, chemical etching of the copper in a HSOor HPOsolution is continued, in this manner avoiding effects of high current density introduced by pattern density.

Method to remove copper without pattern density effect

A new method is provided for the creation of a copper seed interface capability. A first seed layer of copper alloy and a second seed layer of copper is provided over an opening in a layer of dielectric. The opening is filled with copper, the first and second seed layers are annealed.

Barrier free copper interconnect by multi-layer copper seed

A method for alternately electrodepositing and electro-mechanically polishing to selectively fill a semiconductor feature with metal including a) providing an anode assembly and a semiconductor wafer disposed in spaced apart relation including an electrolyte there between the semiconductor wafer including a process surface including anisotropically etched features arranged for an electrodeposition process; b) applying an electric potential across the anode assembly and the semiconductor wafer to induce an electrolyte flow at a first current density to electrodeposit a metal filling portion onto the process surface; c) reversing the electric potential to reverse the electrolyte flow at a second current density to electropolish the process surface in an electropolishing process; and, d) sequentially repeating the steps b and c to electrodeposit at least a second metal filling portion to substantially fill the anisotropically etched features.

Method for integrating an electrodeposition and electro-mechanical polishing process

A new method is provided is creating metal interconnect comprising copper. A first embodiment of the invention provides for the application of a doped layer of copper. A second embodiment of the invention provides for the deposition of a silicon nitride layer as an inter-barrier film over surfaces of an opening created in a layer of dielectric followed by removing the layer of silicon nitride from the bottom of the opening followed by depositing a doped copper-alloy seed layer over surfaces of the opening followed by plating a layer of copper over the copper-alloy seed layer.

Barrier-free copper interconnect

A method of fabricating a planarized metal structure comprising the following steps. A structure is provided. A patterned dielectric layer is formed over the structure. The patterned dielectric layer having an opening formed therein and exposing at least a portion of the structure. A first-metal layer is formed over the patterned dielectric layer filling the opening. The first-metal layer including at least a doped metal portion adjacent the patterned dielectric layer. The doped metal portion being doped with a second-metal. The structure is annealed to form a second-metal oxide layer adjacent the patterned dielectric layer. The first-metal layer and the second-metal oxide layer are planarized using only a electropolishing process to remove the excess of the first-metal layer and the second-metal oxide layer from over the patterned dielectric layer and leaving a planarized metal structure within the opening.

Copper back-end-of-line by electropolish

A method of forming a low resistance metal silicide layer on a narrow width, conductive gate structure, has been developed. After formation of a metal silicide layer on a conductive gate structure via a self-aligned metal silicide (salicide), procedure, unreacted metal is removed via a selective wet etch procedure. Components of the wet etch procedure incorporated in the metal silicide layer, are next removed via a medium temperature&mdash;high vacuum anneal procedure. Removal of the wet etch components incorporated in the metal suicide layer allow a final anneal procedure to convert the metal silicide layer to a lower resistance metal silicide layer, without voids or agglomerated regions of metal silicide which may have formed during the final anneal if the incorporated wet etch components had not been removed.

Method to reduce metal silicide void formation

A method of forming a protective layer included in a metal filled semiconductor feature including providing a substrate including an insulating dielectric material having an anisotropically etched opening for forming a semiconductor feature; conformally depositing over the semiconductor feature at least one metal layer to substantially fill the semiconductor feature at least a portion of the at least one metal layer containing dopant impurities; and, thermally treating the substrate for a time period sufficient to redistribute the dopant impurities to preferentially collect along the periphery of the at least one metal layer.

Growing community of inventors

Hsinchu, Taiwan

Winston Shue