Marvellworld Trade Ltd.

Marvell International Limited

Degirum Corporation

Marvell Asia Pte., Ltd.

Winston Lee

Peter W Lee

Runzi Chang

Pantas Sutardja

Albert M Wu

Chien-Chuan Wei

Sehat Sutardja

Kit Sang Tam

Chorng-Lii Liou

Donald Robert Pannell

Jason T Su

Ha Soo Kim

Moon-Hae Son

Zining Wu

Shashi Kiran Chilappagari

Robert D Bateman

Donald Lee

Kresten V McGrath

David Lippincott

Yuntian Chen

A computer system including a plurality of SIMD engines and a corresponding plurality of output register sets. Operand A register file stores one or more Operand A values, each including a plurality of operand words. Operand B register file stores one or more Operand B values, each including a plurality of operand words. Operand A distribution circuit receives an Operand A value from the Operand A register file, and selectively routes one or more of the operand words of the received Operand A value to create a plurality of input Operand A values, which are selectively routed to the SIMD engines. Operand B distribution circuit receives one or more Operand B values from the Operand B register file, and selectively routes one or more of the operand words of the Operand B value(s) to create a plurality of input Operand B values, which are selectively routed to the SIMD engines.

Method and apparatus for performing matrix multiplication

A permutated ring network includes a plurality of bi-directional source-synchronous ring networks, each having a plurality of data transport stations, and a plurality of communication nodes. Each of the communication nodes is coupled to one of the data transport stations in each of the plurality of bi-directional source-synchronous ring networks.

Permutated ring network

A method for packaging an integrated circuit including a first semiconductor device and a second semiconductor device arranged on a substrate includes calculating parameters of a forming gas based on each of a curing temperature and an estimate of a surface trap density associated with the integrated circuit, dispensing a molding compound over the first semiconductor device, the second semiconductor device, and the substrate, and curing the molding compound in accordance with the curing temperature while flowing the forming gas in accordance with the calculated parameters.

Methods and systems for packaging an integrated circuit

A cascaded clock ring network includes a clock path that transmits a source clock through series-connected processing nodes, from a first processing node to a last processing node. A data path transmits data through the processing nodes in response to the transmitted source clock, from the first processing node to the last processing node. The last processing node provides the transmitted source clock as an end clock signal, and provides the transmitted data as end data values. The end data values are written into a FIFO memory in response to the end clock signal. The end data values are subsequently read from the FIFO memory using the source clock signal, and are provided to the first processing node. A synchronizing circuit ensures that a plurality of end data values are initially written into the FIFO memory before an end data value is read from the FIFO memory.

System and methods for completing a cascaded clock ring bus

The present disclosure describes methods and apparatuses for fabricating integrated-circuit (IC) die with tilted patterning. In some aspects, mandrels are fabricated on a material stack and occlude portions of a layer of material from a field of energy radiated at an angle of incidence relative to the mandrels. The occluded portions of the layer of material can be used to mask an underlying film to create a film pattern on a substrate of the IC die. These methods and apparatuses may enable the fabrication of IC die with features that are smaller in size than those afforded by conventional lithography processes.

Methods and apparatus for fabricating IC chips with tilted patterning

A semiconductor device comprises a first conductive material, a contact, an a magnetic tunneling junction positioned between the first conductive material and the contact. The semiconductor device further comprises a spacer that is positioned between the first conductive material and the contact and surrounds at least a portion of the magnetic tunneling junction. The spacer comprises spacer material that has at least some etch selectivity compared to a dielectric material that surrounds at least a portion of the first conductive material.

MRAM structure for efficient manufacturability

The present disclosure describes apparatuses and methods for manufacturing programmable memory devices with optimized gate oxide thickness. In some aspects, lithography masks are used to fabricate oxide gates for programmable memory devices of an integrated-circuit (IC) die that are thinner than oxide gates fabricated for processor core devices of the IC die. In other aspects, lithography masks are used to fabricate oxide gates for the programmable memory devices of the IC die such that they are thicker than the oxide gates fabricated for the processor core devices of the IC die. By so doing, the programmable memory devices can be manufactured with optimized gate oxide thickness that may reduce programming voltage or increase device reliability of the programmable memory devices.

Fabricating memory devices with optimized gate oxide thickness

A plurality of synchronization FIFOs receive input data streams from corresponding transmitting agents. Data is written to the synchronization FIFOs based on write clock signals provided by the corresponding transmitting agents. An arbitration circuit reads data from the synchronization FIFOs based on an asynchronous local clock signal. A minimum number of entries (S) of each synchronization FIFO is specified by a number of entries required to synchronize the stored data to the local clock signal. Smay further be specified by: a number of entries required to store data during a threshold time period that a throughput of the input data streams may exceed a read data throughput enabled by the local clock signal; a number of entries required to store the data during a flow control response time; and a number of entries read from the synchronization FIFO during the threshold time period and the flow control response time.

System and method for asynchronous, multiple clock domain data streams coalescing and resynchronization

A method for packaging semiconductor devices in a chamber includes arranging a carrier substrate including a first semiconductor device and a second semiconductor device within the chamber, flowing a molding compound into the chamber to cover surfaces of the first semiconductor device, the second semiconductor device, and the carrier substrate, and flowing a forming gas into the chamber while curing the molding compound. The forming gas includes a reactive gas configured to react with the first semiconductor device and the second semiconductor device during curing.

Methods and systems for packaging semiconductor devices to improve yield

The present disclosure includes systems and techniques relating to methods and systems that improve yield in multiple chips integration processes. In some implementations, a method includes providing, in a chamber, a first integrated circuit chip and a second integrated circuit chip supported on a carrier, flowing a molding compound to cover the first integrated circuit chip, the second integrated circuit chip, and the carrier; and flowing a forming gas into the chamber while curing the molding compound.

Methods and systems to improve yield in multiple chips integration processes

In some implementations, a method of fabricating an integrated circuit includes obtaining first data for a first chip containing a first version of the integrated circuit, determining that a transistor should be coupled with another transistor, selecting one or more masks for coupling the transistor with the other transistor to adjust the threshold voltage of the transistor, obtaining second data for a second chip containing a second version of the integrated circuit, determining that the second version of the integrated circuit meets one or more requirements, and preparing a final integrated circuit design for production based on the second version of the integrated circuit.

Integrated circuit manufacturing process for aligning threshold voltages of transistors

Instructions to be executed by a processing system are fetched from a memory. Respective age tags are assigned to the instructions such that each of the age tags indicates an age of the corresponding instruction in the processing system. A respective physical register is allocated to each destination logical register referenced by each instruction. The respective age tags assigned to the instructions are written to respective physical registers allocated to the destination logical registers of the instructions, and to a buffer configured to maintain a program order of the instructions. The instructions are executed by the processing system. Executing the instructions includes executing at least some of the instructions in an order different from the program order of the instructions. The age tags in the buffer are used to retire executed instructions in a same order as the program order of the instructions.

Banked physical register data flow architecture in out-of-order processors

Systems and methods described herein provide a memory cell circuit. The memory cell circuit includes a first internal node communicatively coupled to a first write bit line via a first write pass gate, and a second internal node communicatively coupled to a second write bit line via a second write pass gate. The memory cell circuit further includes a first read bit line connected to a first read pass gate and a first transistor, and a second read bit line connected to a second read pass gate and a second transistor. The first internal node is decoupled from the first read bit line by the first transistor, and the second internal node is decoupled from the second read bit line by the second transistor when a write operation and a read operation occur at the same time.

Systems and methods for a high performance memory cell structure

In a method of executing instructions in a processing system, respective global age tags are assigned to each of the one or more instructions fetched for processing by the processing system. Each global age tag indicates an age of the corresponding instruction in the processing system. Respective physical registers in a physical register file are allocated to each destination logical register referenced by each instruction. The respective global age tags are written to the in respective physical registers allocated to the destination logical registers of the instructions. The instructions are executed by the processing system. At least some of the instructions are executed in an order different from a program order of the instructions.

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Palo Alto, CA, United States of America

Winston Lee