Xilinx, Inc.

Winson Lin

Hongtao Zhang

Yohan Usthavia Frans

Geoffrey Zhang

Yu Xu

Kun-Yung Chang

Zhaoyin D Wu

Hsung Jai Im

Alan C Wong

Christopher J Borrelli

Jinyung Namkoong

Caleb S Leung

Arianne Roldan

Geoff Zhang

Parag Upadhyaya

Ronan Sean Casey

Stanley Yuanshih Chen

Ankur Jain

Yi Zhuang

Yanfei Chen

Jin Namkoong

An example method for clock and data recovery (CDR) includes generating, in a set of slicers of a receiver, in addition to a data signal and a first error signal, at least one additional error signal. The method further includes receiving, at a frequency detector (FD) of a CDR unit of the receiver, the data signal, the first error signal, and the at least one additional error signal, and processing them to generate a FD output. The method still further includes multiplying the FD output by a user-defined FD gain, and adding the FD output, as multiplied by the FD gain, in a frequency path of the CDR unit.

Frequency detector for clock data recovery

Embodiments herein describe correcting nonlinearity in a Digital-to-Time Converter (DTC) by relaxing a DTC linearity requirement, which results in the correction being co-adapted with a DTC gain calibration loop which can operate in parallel with a DTC integral nonlinearity (INL) correction loop. In one embodiment, the DTC gain calibration loop and the DTC INL correction loop are constrained when determining a nonlinearity correction code to improve the likelihood they converge. Once determined, the nonlinearity correction code can be combined with an digital code output by a time-to-digital converter (TDC) to generate a phase difference between a reference clock and a feedback clock.

DTC nonlinearity correction

An example method of clock and data recovery (CDR) includes adding a pre-defined offset to an output of a phase detector (PD) of a CDR circuit, and loading an accumulator of a frequency loop of the CDR circuit with a pre-defined load value. The method further includes detecting the phase of an incoming signal using a PD, and determining that the CDR has locked onto a real lock point. In some examples, the method further includes determining that the CDR has locked on a real lock point, and, in response to the determination, modifying the pre-defined offset to equal zero.

Phase detector offset to resolve CDR false lock

A circuit for determining data error spacing in a data transmitter is disclosed. The circuit comprises a counter; encoding logic configured to receive an output of the counter, wherein the encoding circuit enables generating error spacing information; and a storage element configured to receive an output of the encoding logic.

Circuit for and method of determining error spacing in an input signal

Apparatus(es) and method(s) for CDR are described. In a CDR circuit, there is a bang-bang phase detector ('BBPD'), a baud-rate phase detector ('BRPD'), a multiplexer, and a control circuit. The BBPD, configured to receive data and crossing samples, generates a first result indicating a first phase difference between data and crossing samples. The BRPD, configured to receive data and peak samples, generates a second result indicating a second phase difference between data and peak samples. The multiplexer is configured to select either such result as a phase-detect output for a mode of operation. A control circuit is configured to clear a metastable state: for receipt of the first detect result, check for dithering, determine a direction for phase adjustment responsive to detection of the dithering, and provide a phase adjustment in the direction; and for receipt of the second detect result, operate to use the second phase difference generated.

Clock-data recovery circuit with metastability detection and resolution

A circuit for receiving a signal in an integrated circuit is described. The circuit comprises a sampler configured to receive an input data signal, wherein the sampler generates sampled data and a recovered clock; a clock and data recovery circuit configured to receive the sampled data and the recovered clock and to generate a phase interpolator code; and a phase interpolator configured to receive the phase interpolator code; wherein the phase interpolator generates multiple phase interpolator control signals during a clock cycle based upon the phase interpolator code generated for the clock cycle.

Circuit for and method of receiving a signal in an integrated circuit device

A receiver circuit for receiving data is described. The receiver circuit comprises a phase detector configured to receive an input data signal; a frequency path circuit configured to receive an output of the phase detector; and a false lock detection circuit configured to receive the output of the phase detector and an output of the frequency path circuit; wherein the false lock detection circuit detects a false lock of the receiver circuit to the input data signal based upon an output of the phase detector and provides a frequency offset to the frequency path circuit. A method of receiving data is also described.

Data receiver circuit and method of receiving data

An example method of capturing an error distribution data for a serial channel includes: receiving a signal from the serial channel at a receiver in an integrated circuit (IC), the signal encoding data using pulse amplitude modulation (PAM) scheme having more than two levels; determining a plurality of symbols from the signal, each of the plurality of symbols encoding a plurality of bits; comparing the plurality of symbols with a plurality of expected symbols to detect a plurality of symbol errors; generating the error distribution data by accumulating numbers of the plurality of symbol errors across a plurality of bins based error type; and transmitting the error distribution data from the receiver to a computing system for processing.

Pam multi-level error distribution signature capture

An example apparatus includes an input circuit including a first adder and a first multiplier, the first adder configured to level-shift an input signal by an amount and the first multiplier configured to multiply output of the adder by a factor. The apparatus further includes a multi-stage noise shaping (MASH) circuit having an input coupled to the first multiplier. The apparatus further includes an output circuit including a second multiplier and a second adder, the second multiplier configured to multiply output of the MASH circuit by a reciprocal of the factor and the second adder configured to level-shift output of the second multiplier by an inverse of the amount.

Delta-sigma modulator having expanded fractional input range

A clock and data recovery (CDR) circuit includes a phase detector, a digital loop filter, and a lock detector. The phase detector generates a phase detect result signal in response to phase detection of a plurality of samples. The plurality of samples are generated by sampling a received signal based on a sampling clock a sampling clock provided by a phase interpolator. The digital loop filter includes a phase path and a frequency path for providing a phase path correction signal and a frequency path correction signal based on the phase detect result signal respectively. A phase interpolator code generator generates a phase interpolator code for controlling the phase interpolator based on the phase path correction signal and frequency path correction signal. The lock detector generates a lock condition signal based on the frequency path correction signal, the lock condition signal indicating a lock condition of the CDR circuit.

Systems and methods for clock and data recovery

A clock and data recovery (CDR) circuit includes a phase detector, a frequency accumulator, and a sequencer circuit. The phase detector generates a phase detect result signal in response to phase detection of a plurality of samples, which are generated by sampling a first data signal from a receiver using a sampling clock. The frequency accumulator accumulates, using a frequency register, frequency offset information from the phase detect result signal to generate an accumulated total. The frequency offset information is associated with a frequency difference between a first reference clock of the receiver and a second reference clock associated with the first data signal. The accumulated total is stored in the frequency register and provided from the frequency register for updating the sampling clock. The sequencer circuit is configured to perform a reset operation to reset the accumulated total in the frequency register based on a sequence of sequence elements.

An example method of clock and data recovery in a receiver includes generating data samples and crossing samples of a received signal based on a data clock signal and a crossing clock signal, respectively, which are derived from a sampling clock signal; adjusting a phase of the sampling clock signal using a clock and data recovery (CDR) circuit based on the data samples and the crossing samples; adjusting relative phase between the data clock signal and the crossing clock signal from a first phase difference to a second phase difference that is less than ninety degrees; and reverting the relative phase between the data clock signal and the crossing clock signal to the first phase difference after a threshold time period.

Temporal change in data-crossing clock phase difference to resolve meta-stability in a clock and data recovery circuit

An example method of clock and data recovery in a receiver includes generating data samples and crossing samples of a received signal based on a data phase and a crossing phase, respectively, of a sampling clock supplied by a phase interpolator in the receiver; generating a phase detect result signal in response to phase detection of the data samples and the crossing samples; filtering the phase detect result signal to generate a phase interpolator code, the phase interpolator generating the sampling clock based on the phase interpolator code; determining an average phase detect result from the phase detect result signal; and adjusting the phase interpolator code in response to the average phase detect result being less than a threshold value.

Resolving meta-stability in a clock and data recovery circuit

An apparatus and method relate generally to generation and checking of a quaternary pseudo random binary sequence ('QPRBS'). In an apparatus, there is a pseudo random binary sequence ('PRBS') generator configured to receive a seed of a PRBS to be generated. A mask generator is configured to generate a mask output corresponding to the PRBS. The PRBS generator and the mask generator are both configured for sequential operation with respect to one another. A masking circuit is configured to receive the mask output and the PRBS to bitwise mask the PRBS with the mask output to generate the QPRBS.

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Daly City, CA, United States of America

Winson Lin