Tandem Computers Incorporated

Hewlett-packard Development Company, L.P.

Wing M Chan

David L Griffith

Yie-Fong Dan

Geoffrey I Iswandhi

Kenneth K Chan

Martin W Sanner

James E Korpi

Jay A Zwagerman

Duc Manh Hoang

Steven G Silverman

Zubair Hussain

David L Bernick

James E Smith

An on line serviceable computing system employing a small computer system interface (SCSI) bus architecture connecting two host computers to at least one additional shared device including a termination adapter circuit that can sense when a SCSI termination at the end of the SCSI bus is lost and automatically switch in a new SCSI bus termination to thereby ensure that the bus is terminated at both ends as required for continuous operation.

Automatic bus termination readjustment

Automatic SCSI termination readjustment

In a data processing system, a device controller, configured to control data transfers between a processor unit and a peripheral device on an input/output bus, is provided with apparatus that permits a data transfer cycle to continue until all data has been transferred, or to allow for interruption of the data transfer cycle by another device controller requesting access to the input/output via a request signal. During a data transfer cycle the apparatus resonds to detection of the request signal to interrupt the data transfer cycle after a predetermined number of data words are transferred, permitting access to the input/output bus for other of the device controllers. In absence of the request signal, the apparatus permits the data transfer to continue until all data has been transferred between the peripheral device and the processor unit.

Dynamic burst control for data transfers

Fault tolerant apparatus for generating error correcting code and, simultaneous therewith, checking the correctness of the generation, for blocks of data with which the error correcting code is associated and transmitted to a storage medium. The apparatus includes a pair of programmable control devices configured to selectively operate in one of two modes: A first mode in which data being transferred to the storage medium is monitored for generation of an error correcting code to be associated and stored with each data block, and a second mode in which the data being transferred is monitored for detecting errors that may be contained in the data. During data transmission to the storage device, one of the control devices operates in the first mode, while the other control device operates in the second mode to check operation of the first device. When data is retrieved from the storage device, both control devices operate in the second mode to check the correctness of the data being transferred, and the operability of each other.

Data integrity checking with fault tolerance

In a digital computer system which employs a plurality of host processors, at least two system buses and a plurality of peripheral input/output ports, an input/output system is provided whereby ownership of the input/output channels is shared. The device controller employs a first port controller having a first ownership latch, a second port controller having a second ownership latch, a first bus, a dedicated microprocessor having control over the first bus (the MPU bus), a second, higher-speed bus, a multiple-channel direct memory access (DMA) controller which is a state machine which controls the second bus (the data buffer bus), a bus switch for exchanging data between buses, a multiple device peripheral device interface, namely a Small Computer System Interface (SCSI), and at least provision for interface with data communication equipment (DCEs) or data terminal equipment (DTEs). The DMA controller arbitrates data bus usage and can allocate alternate bus clock cycles in response to requests to exchange data and is capable of supporting overlapping transfers. The microprocessor is allowed access to the data buffer bus only if the data buffer bus is not in use for data transfer. The latches associated with each port grant ownership to either port or both ports allowing data exchange between addressed peripheral devices and requesting ports.

Input/output system for multiprocessors

Growing community of inventors

Fremont, CA, United States of America

Wing M Chan